发明公开
EP2096786A3 Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation 有权
的指令组合,包括执行用于转换的隔离转换序列的指令

  • 专利标题: Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation
  • 专利标题(中): 的指令组合,包括执行用于转换的隔离转换序列的指令
  • 申请号: EP09250543.7
    申请日: 2009-02-27
  • 公开(公告)号: EP2096786A3
    公开(公告)日: 2012-01-25
  • 发明人: Gueron, ShaySperber, Zeev
  • 申请人: Intel Corporation
  • 申请人地址: 2200 Mission College Boulevard Santa Clara, CA 95052 US
  • 专利权人: Intel Corporation
  • 当前专利权人: Intel Corporation
  • 当前专利权人地址: 2200 Mission College Boulevard Santa Clara, CA 95052 US
  • 代理机构: Beresford, Keith Denis Lewis
  • 优先权: US40214 20080229
  • 主分类号: H04L9/06
  • IPC分类号: H04L9/06
Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation
摘要:
The Advanced Encryption Standard (AES) is defined by FIPS Publication #197 (2001). From the cryptographic perspective, AES is widely believed to be secure and efficient, and is therefore broadly accepted as the standard for both government and industry applications.
If fact, almost any new protocol requiring symmetric encryption supports AES, and many existing systems that were originally designed with other symmetric encryption algorithms are being converted to AES. Given the popularity of AES and its expected long term importance, improving AES performance and security has significant benefits for the PC client and server platforms.
A new set of instructions is introduced into the next generation of processors family, starting from the processor called Westmere. The new architecture has six instructions: four instructions (AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and decryption, and the other two (AESIMC and AESKEYGENASSIST) support the AES key expansion. In addition, all six instructions are promoted to a non-destructive destination version (namely VAESENC, VAESENCLAST, VAESDEC, VAESDELAST, VAESIMC, and VAESKEYGENASSIST.
Together, these instructions provide full hardware support for AES, offering high performance, enhanced security, and a great deal of software usage flexibility.
The new AES instructions can support AES encryption and decryption with each one of the standard key lengths (128, 192, and 256 bits), using the standard block size of 128 bits (and potentially also other block sizes for generalized variants such as the RIJNDAEL algorithms). They are well suited to all common uses of AES, including bulk encryption/decryption using cipher modes such as ECB, CBC and CM, data authentication using CBC-MACs, random number generation using algorithms such as CTR-DPBG, and authenticated encryption using modes such as GCM.
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