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    Device, system, and method for solving systems of linear equations using parallel processing
    1.
    发明公开
    Device, system, and method for solving systems of linear equations using parallel processing 审中-公开
    装置，系统和方法，用于使用并行处理求解线性方程组

    公开(公告)号：EP2112602A3

    公开(公告)日：2012-11-07

    申请号：EP09251173.2

    申请日：2009-04-24

    申请人： Intel Corporation

    发明人： Myaskouvskey, Artiom ,  Gueron, Shay

    IPC分类号： G06F17/12 ,  H04N7/01 ,  H04N5/14

    CPC分类号： G06F17/12 ,  H04N5/145 ,  H04N7/0127

    摘要： A method, apparatus and system for multiplying a matrix by a vector, for example, video interpolation (other applications are contemplated). The matrix may be a representation of a large and sparse system of linear equations. The large and sparse system of linear equations may be used to estimate motion between frames of a video file for converting frame rates. The vector may be a first estimation of a solution to the system of linear equations. The matrix may be multiplied by elements of the vector in an order different from the order in which the elements are arranged in the vector. Elements in the vector may be multiplied in parallel. A second vector estimation of the solution to a system of linear equations may be a product of the multiplying. The solution to the system of linear equations may be set, for example, when the first and second vector estimations differ by less than a predetermined amount. Other embodiments are described and claimed.

    A technique for Aacelerating characteristic 2 Eeliptic curve cryptography
    2.
    发明公开
    A technique for Aacelerating characteristic 2 Eeliptic curve cryptography 有权
    对于Beschlenigung一种技术特征2的椭圆曲线加密

    公开(公告)号：EP2075689A3

    公开(公告)日：2010-12-22

    申请号：EP08171398.4

    申请日：2008-12-11

    申请人： Intel Corporation

    发明人： Gueron, Shay ,  Kounvais, Michael

    IPC分类号： G06F7/72 ,  H04L9/30

    CPC分类号： G06F7/725 ,  G06F7/724 ,  H04L9/3026 ,  H04L9/3066 ,  H04L2209/80

    摘要： In this invention we describe a novel approach for speeding up the computations of characteristic 2 elliptic curve cryptography. Using a projective space such as the Lopez-Dahab space for representing point coordinates we accelerate point additions and point doublings by introducing a novel way for multiply elements in finite fields of the form GF(2 m ). Our technique uses a CPU instruction for carry-less multiplication (GFMUL) and single iteration Karatsub a-like formulae for computing the carry-less product of large degree polynomials in GF(2 m ). It then performs the reduction of the carry-less product of these polynomials by taking into account the fact that many curves specify fields with irreducible polynomials which are sparse. For example NIST curves specify polynomials with either three terms (trinomials) or five terms (pentanomials). We demonstrate results from a prototype implementation showing that our technique speeds up Elliptic Curve Diffie Hellman based on the NIST B-233 curve by 55% in software on a 3.6 GHz Pentium 4 processor. If a 3 clock latency GFMUL instruction is introduced to the CPU then the acceleration factor becomes 5.2X. We also show that further software optimizations have the potential to further increase the speedup beyond 10x.

    Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
    3.
    发明公开
    Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation 有权
    用于优化操作的并行模式下的数据加密标准加密和解密的方法和设备

    公开(公告)号：EP2096787A3

    公开(公告)日：2010-12-01

    申请号：EP09250544.5

    申请日：2009-02-27

    申请人： Intel Corporation

    发明人： Gueron, Shay ,  Gradstein, Amit ,  Sperber, Zeev

    IPC分类号： H04L9/06

    CPC分类号： H04L9/0631 ,  G06F9/30007 ,  H04L2209/125

    摘要： The Advanced Encryption Standard (AES) is defined by FIPS Publication #197 (2001). From the cryptographic perspective, AES is widely believed to be secure and efficient, and is therefore broadly accepted as the standard for both government and industry applications.
    If fact, almost any new protocol requiring symmetric encryption supports AES, and many existing systems that were originally designed with other symmetric encryption algorithms are being converted to AES. Given the popularity of AES and its expected long term importance, improving AES performance arid security has significant benefits for the PC client and server platforms.
    A new set of instructions is introduced into the next generation of processors family, starting from the processor called Westmere. The new architecture has six instructions: four instructions (AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and decryption, and the other two (AESIMC and AESKEYGENASSIST) support the AES key expansion. In addition, all six instructions are promoted to a non-destructive destination version (namely VAESENC, VAESENCLAST, VAESDEC, VAESDELAST, VAESIMC, and VAESKEYGENASSIST.
    Together, these instructions provide full hardware support for AES, offering high performance, enhanced security, and a great deal of software usage flexibility.
    The new AES instructions can support AES encryption and decryption with each one of the standard key lengths (128,192, and 256 bits), using the standard block size of 128 bits (and potentially also other block sizes for generalized variants such as the RIJNDAEL algorithms). They are well suited to all common uses of AES, including bulk encryption/decryption using cipher modes such as ECB, CBC and CM, data authentication using CBC-MACs, random number generation using algorithms such as CTR-DPBG, and authenticated encryption using modes such as GCM.

    A technique for Aacelerating characteristic 2 Eeliptic curve cryptography
    4.
    发明公开
    A technique for Aacelerating characteristic 2 Eeliptic curve cryptography 有权
    对于Beschlenigung一种技术特征2的椭圆曲线加密

    公开(公告)号：EP2075689A2

    公开(公告)日：2009-07-01

    申请号：EP08171398.4

    申请日：2008-12-11

    申请人： Intel Corporation

    发明人： Gueron, Shay ,  Kounvais, Michael

    IPC分类号： G06F7/72 ,  H04L9/30

    CPC分类号： G06F7/725 ,  G06F7/724 ,  H04L9/3026 ,  H04L9/3066 ,  H04L2209/80

    摘要： In this invention we describe a novel approach for speeding up the computations of characteristic 2 elliptic curve cryptography. Using a projective space such as the Lopez-Dahab space for representing point coordinates we accelerate point additions and point doublings by introducing a novel way for multiply elements in finite fields of the form GF(2 m ). Our technique uses a CPU instruction for carry-less multiplication (GFMUL) and single iteration Karatsub a-like formulae for computing the carry-less product of large degree polynomials in GF(2 m ). It then performs the reduction of the carry-less product of these polynomials by taking into account the fact that many curves specify fields with irreducible polynomials which are sparse. For example NIST curves specify polynomials with either three terms (trinomials) or five terms (pentanomials). We demonstrate results from a prototype implementation showing that our technique speeds up Elliptic Curve Diffie Hellman based on the NIST B-233 curve by 55% in software on a 3.6 GHz Pentium 4 processor. If a 3 clock latency GFMUL instruction is introduced to the CPU then the acceleration factor becomes 5.2X. We also show that further software optimizations have the potential to further increase the speedup beyond 10x.

    摘要翻译： 在本发明中，我们描述了用于加速特性2椭圆曲线密码学的计算的新方法。 使用射影空间：诸如用于表示点洛佩兹-Dahab的空间中的坐标由我们在形式GF（2 m）上的有限域乘法元件引入一种新颖的方式加速点加法和点倍增。 我们的技术使用用于进位少的乘法（GFMUL）和单次迭代Karatsub一个CPU指令状式餐饮用于计算在GF（2 m）上的很大程度的多项式的进位少的乘积。 然后，它执行合成多项式的进位少的乘积的通过考虑到factthat许多曲线指定与不可约多项式哪些是稀疏字段的降低。 对于实施例NIST曲线指定与无论三个术语（三项式）或五个术语（pentanomials）多项式。 我们证明从原型实现显示结果做了基于55％的软件运行在3.6 GHz的奔腾4处理器的NIST B-233曲线上我们的技术加快椭圆曲线Diffie-Hellman。 如果3个时钟延迟GFMUL指令引入到CPU则加速因子5.2倍而成。 所以我们做了展示更多的软件优化必须增加进一步加速超过10倍的潜力。

    Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation
    10.
    发明公开
    Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation 有权
    的指令组合，包括执行用于转换的隔离转换序列的指令

    公开(公告)号：EP2096786A3

    公开(公告)日：2012-01-25

    申请号：EP09250543.7

    申请日：2009-02-27

    申请人： Intel Corporation

    发明人： Gueron, Shay ,  Sperber, Zeev

    IPC分类号： H04L9/06

    CPC分类号： H04L9/0681 ,  G06F9/30007 ,  G06F21/75 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

    摘要： The Advanced Encryption Standard (AES) is defined by FIPS Publication #197 (2001). From the cryptographic perspective, AES is widely believed to be secure and efficient, and is therefore broadly accepted as the standard for both government and industry applications.
    If fact, almost any new protocol requiring symmetric encryption supports AES, and many existing systems that were originally designed with other symmetric encryption algorithms are being converted to AES. Given the popularity of AES and its expected long term importance, improving AES performance and security has significant benefits for the PC client and server platforms.
    A new set of instructions is introduced into the next generation of processors family, starting from the processor called Westmere. The new architecture has six instructions: four instructions (AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and decryption, and the other two (AESIMC and AESKEYGENASSIST) support the AES key expansion. In addition, all six instructions are promoted to a non-destructive destination version (namely VAESENC, VAESENCLAST, VAESDEC, VAESDELAST, VAESIMC, and VAESKEYGENASSIST.
    Together, these instructions provide full hardware support for AES, offering high performance, enhanced security, and a great deal of software usage flexibility.
    The new AES instructions can support AES encryption and decryption with each one of the standard key lengths (128, 192, and 256 bits), using the standard block size of 128 bits (and potentially also other block sizes for generalized variants such as the RIJNDAEL algorithms). They are well suited to all common uses of AES, including bulk encryption/decryption using cipher modes such as ECB, CBC and CM, data authentication using CBC-MACs, random number generation using algorithms such as CTR-DPBG, and authenticated encryption using modes such as GCM.