A semiconductor memory device comprises a plurality of memory cells; a plurality of bit and word lines; a plurality of sense amplifiers for sensing and amplifying signals from the bit lines; a plurality of column access devices for coupling the bit lines to a data line of the memory device; delay circuitry for providing a delayed word line timing pulse and a further delayed word line timing pulse; and enable circuitry for enabling the sense amplifier in response to the delayed word line timing pulse and the column access device in response to the further delayed word line timing pulse.