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    Clocked memory with latching predecoder circuitry
    5.
    发明公开
    Clocked memory with latching predecoder circuitry 审中-公开
    锁存预解码器电路的时钟存储器

    公开(公告)号：EP2672485A3

    公开(公告)日：2017-11-01

    申请号：EP13169562.9

    申请日：2013-05-28

    申请人： NXP USA, Inc.

    发明人： Ramamurthy, Hema ,  Ramaraju , Ravindraraj

    IPC分类号： G11C7/22 ,  G11C8/08 ,  G11C8/18 ,  G11C8/10

    CPC分类号： G11C8/10 ,  G11C7/222 ,  G11C8/08 ,  G11C8/18

    摘要： A memory (10) includes a memory array (12) having a plurality of word lines (WL), a plurality of latching predecoders (18), and word line driver logic (14). Each latching predecoder receives a clock signal (CLK) and a plurality of address signals (A0, A0b) and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.

    摘要翻译： 存储器（10）包括具有多个字线（WL），多个锁存预译码器（18）和字线驱动器逻辑（14）的存储器阵列（12）。 响应于时钟信号的时钟周期的第一沿，每个锁存预解码器接收时钟信号（CLK）和多个地址信号（A0，A0b）并且锁存多个地址信号的逻辑功能的结果，以及 响应于时钟信号的第一时钟周期的第二边缘提供预定值，其中，响应于第二边缘，多个锁存预解码器中的每个锁存解码器提供相同的预定值。 字线驱动器逻辑响应于锁存结果而选择性地激活多个字线中的选定字线。

    MEMORY INTERFACE SIGNAL REDUCTION
    6.
    发明公开
    MEMORY INTERFACE SIGNAL REDUCTION 有权
    SPEICHERSCHNITTSTELLEN-SIGNALREDUKTION

    公开(公告)号：EP3131095A1

    公开(公告)日：2017-02-15

    申请号：EP16182200.2

    申请日：2011-12-16

    申请人： Intel Corporation

    发明人： Nale, Bikk

    IPC分类号： G11C7/10 ,  G06F13/16 ,  G11C7/22 ,  G11C8/18

    CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/109 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/105

    摘要： In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，控制器包括存储器激活引脚，一个或多个组合的存储器命令/地址信号引脚，以及选择电路，其适于响应于存储器激活引脚选择一个或多个组合存储器命令/地址信号引脚中的每一个 存储器命令信号或存储器地址信号。 描述和要求保护其他实施例。

    Clocked memory with word line activation during a first portion of the clock cycle
    9.
    发明公开
    Clocked memory with word line activation during a first portion of the clock cycle 审中-公开
    Getaktete Speicher mit Wortzeilenaktivierungwährendeines Ersten Teils des Taktzyklus

    公开(公告)号：EP2672486A2

    公开(公告)日：2013-12-11

    申请号：EP13169553.8

    申请日：2013-05-28

    申请人： Freescale Semiconductor, Inc.

    发明人： Ramamurthy, Hema ,  Ramaraju, Ravindraraj

    IPC分类号： G11C8/08 ,  G11C8/18 ,  G11C7/22

    CPC分类号： G11C8/10 ,  G11C7/222 ,  G11C8/08 ,  G11C8/18

    摘要： A memory (10) includes a plurality of latching predecoders (20, 22, 24, 26), each including a first transistor (30, 136) coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor (32, 108) coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor (34, 110) coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor (36, 112) coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor (38, 114) coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value (A6A7b) during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.

    摘要翻译： 存储器（10）包括多个锁存预解码器（20,22,24,26），每个锁存预解码器包括耦合在电源电压和锁存器之间并具有耦合到时钟信号的控制电极的第一晶体管（30,136） ; 耦合到所述第一晶体管并且具有耦合到第一地址位信号的控制电极的第二晶体管（32,108） 耦合到所述第二晶体管并且具有耦合到第二地址位信号的控制电极的第三晶体管（34,110） 第四晶体管（36,112），其耦合到所述第三晶体管并具有耦合到所述时钟信号的延迟和反相形式的控制电极; 第五晶体管（38,114），耦合在所述第四晶体管和地之间并且具有耦合到所述时钟信号的控制电极; 以及在时钟周期的第二部分期间在时钟信号的时钟周期的第一部分和预定逻辑电平期间提供预解码值（A6A7b）的输出。