发明公开
- 专利标题： High performance system-on-chip using post passivation process
- 专利标题（中）： 采用后钝化工艺的高性能系统级芯片
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申请号： EP10012703.4申请日： 2001-08-27
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公开(公告)号： EP2287890A2公开(公告)日： 2011-02-23
- 发明人: Lin, Mou-Shiung
- 申请人： Megica Corporation
- 申请人地址： Rm 301/302, No. 47, Park 2nd Road Science-Based Industrial Park Hsinchu TW
- 专利权人： Megica Corporation
- 当前专利权人： Megica Corporation
- 当前专利权人地址： Rm 301/302, No. 47, Park 2nd Road Science-Based Industrial Park Hsinchu TW
- 代理机构： Schuffenecker, Thierry
- 优先权： US721722 20001127
- 主分类号： H01L21/02
- IPC分类号： H01L21/02 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L21/60 ; H01L27/08
摘要：
An integrated circuit chip comprising:
- a silicon substrate;
- a first dielectric layer over said silicon substrate;
- a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated gold;
- a second dielectric layer between said first and second metal layers;
- a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises a nitride layer; and
- a third metal layer over said separating layer, wherein said third metal layer comprises at least a portion, vertically over said separating layer, of an inductor, wherein said third metal layer comprises electroplated gold.
- a silicon substrate;
- a first dielectric layer over said silicon substrate;
- a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated gold;
- a second dielectric layer between said first and second metal layers;
- a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises a nitride layer; and
- a third metal layer over said separating layer, wherein said third metal layer comprises at least a portion, vertically over said separating layer, of an inductor, wherein said third metal layer comprises electroplated gold.
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