An amplifier 100 has an input 108 for receiving a signal to be amplified and an output 110 for outputting an amplified signal. The amplifier 100 comprises a main amplification stage 102, an auxiliary amplification stage 104 and a controller 106. The main amplification stage 102 comprises a main amplification circuit 200 and the auxiliary amplification stage 104 comprises an auxiliary amplification circuit 202. Each of the main amplification circuit 200 and the auxiliary amplification circuit 202 comprises a p-channel metal oxide semiconductor (PMOS) transistor T1, T3 and an n-channel metal oxide semiconductor (NMOS) transistor T2, T4. The PMOS and NMOS transistors T3, T4 of the auxiliary amplification circuit 202 are either identical to the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200 or are scaled down copies of the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200. The auxiliary amplification circuit 202 amplifies the input signal to generate a control signal and the controller 106 controls a function of the amplifier 100 based on the control signal.