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    Method and apparatus for avoiding spurs in chip
    2.
    发明授权
    Method and apparatus for avoiding spurs in chip 有权

    公开(公告)号：EP2849363B1

    公开(公告)日：2018-06-13

    申请号：EP13306263.8

    申请日：2013-09-16

    申请人： ST-Ericsson SA

    发明人： Pineau, Stéphane ,  Harnay, Didier ,  Sittler, François

    IPC分类号： H04B15/04

    CPC分类号： H03L7/1075 ,  H03L7/0802 ,  H04B15/04

    摘要： A method of rejecting spurs within a chip containing analog and digital functions, the spurs being timed by an associated clock signal derived from the output signal of a High Frequency, HF, fractional Phase Locked Loop, PLL, the method comprising: - determining original analog rejection bandwidths associated with the operation of analog functions; - identifying original spurs associated with the operation of the digital functions and capable of affecting the original analog rejection bandwidths directly or indirectly; - obtaining a final analog rejection bandwidth based on the original analog rejection bandwidths; - obtaining final spurs based on the original spurs; - determining a frequency shift of the output frequency of the HF fractional PLL adapted to reject the final spurs from the final analog rejection bandwidth; and, - controlling the HF fractional PLL to shift the output frequency of said HF fractional PLL by the frequency shift.

    POLAR MODULATOR
    7.
    发明授权
    POLAR MODULATOR 有权
    极化调制器

    公开(公告)号：EP2677711B1

    公开(公告)日：2016-06-01

    申请号：EP12172836.4

    申请日：2012-06-20

    申请人： ST-Ericsson SA

    发明人： Visser, Hendrik ,  Heijna, Roeland

    IPC分类号： H04L27/36 ,  H03C5/00 ,  H04W52/02 ,  H04B14/00

    CPC分类号： H04L27/36 ,  H03C5/00 ,  H04B14/008 ,  H04L27/361 ,  H04W52/0209 ,  Y02D70/122

    摘要： A polar modulator (200) comprises a modulation generator (10) arranged to generate phase modulation data and amplitude modulation data; and a phase modulation stage (20) arranged to generate a phase modulated, PM, carrier signal and a PM clock signal, wherein the PM carrier signal has a PM carrier signal frequency and the PM clock signal has a PM clock signal frequency, and the PM carrier signal frequency is higher than the PM clock signal frequency, the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data, and the phase modulation stage (20) comprises an adjustable delay stage (50) arranged to adjust a relative delay between the PM carrier signal and the PM clock signal to a target value. The polar modulator (200) further comprises a re-timing circuit (40) arranged to generate an amplitude modulation, AM, clock signal by re-timing the PM clock signal with the PM carrier signal; an amplitude modulation stage (30) arranged to employ the AM clock signal to clock the amplitude modulation data into the amplitude modulation stage (30) and arranged to amplitude modulate the PM carrier signal with the amplitude modulation data; an error detection stage (60) arranged to generate an indication of a magnitude of a first deviation of the AM clock signal from a target condition; and a control stage (70) arranged to select the target value of the relative delay by determining, by controlling the adjustment of the relative delay by the adjustable delay stage (50), a first value of the relative delay that maximises the magnitude of the first deviation, and applying an offset to the first value of the relative delay.