The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-
n ) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (C
n-1 ,..., C
0 ) in the order of decreasing capacitances starting from the capacitor (C
n-1 ) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b
n-1 ,..., b
0 ) in the digital output word that correspond to the capacitors (C
n-1 ,..., C
0 ) on which the reference voltage (U
L) of a desired value has been obtained, and the value zero is assigned to the other bits.