公开(公告)号：EP2374740A2

公开(公告)日：2011-10-12

申请号：EP11460007.5

申请日：2011-02-21

申请人： Akademia Gomiczo-hutnicza Im. Stanislawa Staszica

发明人： Furmanik, Kazimierz ,  Kalukiewicz, Antoni ,  Kulinowski, Piotr ,  Wieloch, Stanislaw ,  Lasota. Tomasz

IPC分类号： B65G39/09

CPC分类号： B65G39/09

摘要： The roller of belt-conveyor having split bearings, stopper rings, stoppers, compound sealing rings and thrower sealing rings, characterised by that, that it has a smooth metal tube housing (1) both ends of which are closed with flanged hubs (2) made of metal by forging or machining, on external faces (3) of the hubs (2) there are projecting graded half-shafts (4) located on longitudinal axis (5) of the roller, bases for the half-shafts (4) are sockets situated in cylindrical flanges (7) of the hubs (2), on split bearings (8) are situated sleeves (9) provided with stoppers (10) and on the surfaces of the sleeves (9) are made opposite flat cantings (11) which enable mounting the sleeves (9) in forks of the frame of conveyor and said tube housing (1) is connected to the hubs (2) by welding.

摘要翻译： 带式输送机的辊子具有分离轴承，止动环，止动件，复合密封环和抛出机密封环，其特征在于，它具有光滑的金属管壳体（1），其两端用凸缘毂（2）封闭， 通过锻造或加工由金属制成，在轮毂（2）的外表面（3）上存在位于辊的纵向轴线（5）上的突出的渐变半轴（4），用于半轴（4）的基座 是位于轮毂（2）的圆柱形凸缘（7）中的插座，在分离轴承（8）上设置有设置有止动件（10）的套筒（9），并且在套筒（9）的表面上形成与平坦的倾斜 11），其能够将套筒（9）安装在输送机框架的叉中，并且所述管壳体（1）通过焊接连接到轮毂（2）。

公开(公告)号：EP2577408A2

公开(公告)日：2013-04-10

申请号：EP11779494.1

申请日：2011-06-05

申请人： Akademia Gomiczo-hutnicza Im. Stanislawa Staszica

发明人： KOSCIELNIK, Dariusz ,  MISKOWICZ, Marek

IPC分类号： G04F10/00

CPC分类号： G04F10/00 ,  G04F10/005

摘要： The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (C
n-1 ,..., C
0 ) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((C
n-1 ,..., C
0 )) in the order of decreasing capacitances starting from the capacitor (C
n-1 ) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (C
x ) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b
n-1 ,..., b
0 ) in the digital output word that correspond to the capacitors (C
n-1 ,..., C
0 ) on which the reference voltage (U
L ) of a desired value has been obtained, and the value zero is assigned to the other bits.

摘要翻译： 根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1，...，C0）的阵列（A）将时间间隔转换成等于n的位数的数字字， 其特征在于，由控制模块（CM）检测出开始和结束的时间间隔首先映射到由电流源（I）传送的电荷的一部分，并依次累加在电容器（（Cn-1， ...，C0）），从阵列中具有最高电容值的电容器（Cn-1）开始降低电容的顺序，并且当控制模块（CM）检测到时间间隔的结束时，电荷累积 在最近充电的电容器（Cx）中，通过使用电流源（I）连续传送到具有较低电容值的电容器。 基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1分配给这些位（bn-1 ，...，b0）对应于其上已经获得了期望值的参考电压（UL）的电容器（Cn-1，...，C0），并且分配值零 到其他位。

公开(公告)号：EP2577407A2

公开(公告)日：2013-04-10

申请号：EP11779239.0

申请日：2011-06-05

申请人： Akademia Gomiczo-hutnicza Im. Stanislawa Staszica

发明人： KOSCIELNIK, Dariusz ,  MISKOWICZ, Marek

IPC分类号： G04F10/00

CPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/12 ,  H03M1/125 ,  H03M1/466 ,  H03M1/804

摘要： The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-
n ) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (C
n-1 ,..., C
0 ) in the order of decreasing capacitances starting from the capacitor (C
n-1 ) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b
n-1 ,..., b
0 ) in the digital output word that correspond to the capacitors (C
n-1 ,..., C
0 ) on which the reference voltage (U
L) of a desired value has been obtained, and the value zero is assigned to the other bits.

摘要翻译： 将根据本发明的将电压值转换为等于n的位数的数字字的根据本发明的解决方案的特征在于，转换的电压值首先映射到在采样电容器（Cn）中累积的一部分电荷， 在触发输入（InS）的信号的有效状态下，通过使用二进制比例电容器（Cn-1，...）的阵列（A）中的电流源（I），继续重新分配累积电荷部分。 （C0）以从阵列（A）中具有最高电容值的电容器（Cn-1）开始降低电容的顺序。 电荷再分配的过程由控制模块（CM）基于比较器（K1）和（K2）的输出信号而不使用时钟来控制，而值1分配给这些位（bn-1 ，...，b0）对应于其上已经获得了期望值的参考电压（UL）的电容器（Cn-1，...，C0），并且分配值零 到其他位。

公开(公告)号：EP2577409A2

公开(公告)日：2013-04-10

申请号：EP11781674.4

申请日：2011-06-05

申请人： Akademia Gomiczo-hutnicza Im. Stanislawa Staszica

发明人： KOSCIELNIK, Dariusz ,  MISKOWICZ, Marek

IPC分类号： G04F10/00

CPC分类号： H03M1/12 ,  H03M1/466

摘要： The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (C
n-1 ,...,C
o ) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (C
n-1 ,...,C
o ) in the order of decreasing capacitances starting from the capacitor (C
n-1 ) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (C
x ) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b
n-1 ,..., b
0 ) in the digital output word that correspond to the capacitors (C
n-1 ,...,C
o ) on which the reference voltage (U
L ) of a desired value has been obtained, and the value zero is assigned to the other bits.

摘要翻译： 将溶液雅丁于本发明中的电荷的一部分的转换由与数量等于n位通过使用电荷的连续再分配中的数字字的二进制缩放电容器（CN-1的阵列（A）中 ，...，Co）的在没有电荷被外部栅极信号的上在电容器中的栅极信号输入（正在）活动状态期间第一累积的特征在于（C在的级的n-1，...，Co）的 减少从电容器（CN-1），具有在阵列中的最高的电容值，并且当栅极信号的有效状态被终止，在最近充电的电容器（CX）中累积的电荷通过使用依次转印开始电容 电流源（I）到较低的电容值的电容器。 的电荷转移过程是由比较器（K1）和（K2）不使用时钟的输出信号的基础上，所述控制模块（CM），而值之一被分配给合成比特（BN-1控制 ，...，B0）的数字输出字并对应于电容器（C N-1，...，Co）的在其上的基准电压为期望值的（UL）已经获得的，并且零值被分配 到其他位。