发明公开
- 专利标题： MULTI-CORE PROCESSOR SYSTEM, SYNCHRONISATION CONTROL SYSTEM, SYNCHRONISATION CONTROL DEVICE, INFORMATION GENERATION METHOD, AND INFORMATION GENERATION PROGRAMME
- 专利标题（中）： 多用途防护系统，同步通信系统，同步通信系统，信息通信系统
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申请号： EP10856664.7申请日： 2010-08-30
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公开(公告)号： EP2613269A1公开(公告)日： 2013-07-10
- 发明人: YAMASHITA, Koichiro , YAMAUCHI, Hiromasa , SUZUKI, Takahisa , KURIHARA, Koji
- 申请人： Fujitsu Limited
- 申请人地址： 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
- 代理机构： Ward, James Norman
- 国际公布： WO2012029111 20120308
- 主分类号： G06F15/17
- IPC分类号： G06F15/17 ; G06F9/38
摘要：
A CPU (#0) among a multi-core processor, by a detecting unit (502), detects a migration of a thread under execution by a CPU (#M) as a synchronization source core to a CPU (#N) as a synchronization destination core in the multi-core processor. After the detection, the CPU (#0), by an identifying unit (503), refers to a register dependency table (501) and identifies a particular register corresponding to the thread for which migration was detected. After the identification, the CPU (#0), by a generating unit (504), generates synchronization control information identifying the identified particular register and the synchronization destination core. A synchronization controller (505) communicably connected to the multi-core processor acquires the generated synchronization control information from the CPU (#0). The synchronization controller (505) then reads in the value of the particular register obtainable from the synchronization control information from the particular register of the CPU (#M) and writes the read-in value in the particular register of the CPU (#N).
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