发明公开
EP2768015A1 GOLD/SILICON EUTECTIC CHIP SOLDERING METHOD AND TRANSISTOR
审中-公开
EUTEKTISCHES GOLD / SILIZIUM-CHIPLÖTVERFAHRENUND TRANSISTOR
- 专利标题: GOLD/SILICON EUTECTIC CHIP SOLDERING METHOD AND TRANSISTOR
- 专利标题(中): EUTEKTISCHES GOLD / SILIZIUM-CHIPLÖTVERFAHRENUND TRANSISTOR
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申请号: EP13799475.2申请日: 2013-08-02
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公开(公告)号: EP2768015A1公开(公告)日: 2014-08-20
- 发明人: YUN, Lungang , HUANG, An , TIAN, Pengbo
- 申请人: Huawei Technologies Co., Ltd.
- 申请人地址: Huawei Administration Building Bantian, Longgang Shenzhen, Guangdong 518129 CN
- 专利权人: Huawei Technologies Co., Ltd.
- 当前专利权人: Huawei Technologies Co., Ltd.
- 当前专利权人地址: Huawei Administration Building Bantian, Longgang Shenzhen, Guangdong 518129 CN
- 代理机构: Körber, Martin Hans
- 优先权: CN201210562498 20121221
- 国际公布: WO2014094436 20140626
- 主分类号: H01L21/58
- IPC分类号: H01L21/58 ; H01L23/48
摘要:
Relating to electronic components, the present invention provides a method for welding a gold-silicon eutectic chip, and a transistor, to resolve a technical problem in a current gold-silicon eutectic welding method that a cost of a transistor increases because a gold layer electroplated on a chip carrier is relatively thick. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present invention reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.
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