发明公开
- 专利标题: SEMICONDUCTOR CONSTRUCTIONS AND METHODS OF PLANARIZING ACROSS A PLURALITY OF ELECTRICALLY CONDUCTIVE POSTS
- 专利标题(中): 半导体结构和平面化程序之间的若干导电POST
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申请号: EP13760569.7申请日: 2013-02-12
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公开(公告)号: EP2826061A1公开(公告)日: 2015-01-21
- 发明人: GANDHI, Jaspreet, S.
- 申请人: Micron Technology, Inc.
- 申请人地址: 8000 South Federal Way Boise, ID 83716 US
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: 8000 South Federal Way Boise, ID 83716 US
- 代理机构: Somervell, Thomas Richard
- 优先权: US201213418113 20120312
- 国际公布: WO2013138006 20130919
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/304
摘要:
Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.
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