One embodiment relates to a receiver (100) with both decision feedback equalization and on-die instrumentation. A clock data recovery loop (122, 123, 124) obtains a recovered clock signal from an input signal, and a first sampler (126), which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator (134) receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler (148) is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.