公开(公告)号：EP2833552A2

公开(公告)日：2015-02-04

申请号：EP14177855.5

申请日：2014-07-21

申请人： Altera Corporation

发明人： Ke, Yanjing ,  Tran, Thungoc M. ,  Ding, Weiqi ,  Shen, Jie ,  Liu, Xiong ,  Raman, Sangeeta ,  Li, Peng

IPC分类号： H03L7/00 ,  H04L7/033

CPC分类号： H04L25/03057 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L2025/03356

摘要： One embodiment relates to a receiver (100) with both decision feedback equalization and on-die instrumentation. A clock data recovery loop (122, 123, 124) obtains a recovered clock signal from an input signal, and a first sampler (126), which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator (134) receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler (148) is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及具有判决反馈均衡和管芯仪表的接收器（100）。 时钟数据恢复循环（122,123,124）从输入信号获得恢复的时钟信号，并且由恢复的时钟信号触发的第一采样器（126）从输入信号产生恢复的数据信号。 相位插值器（134）接收恢复的时钟信号并产生相位插值的时钟信号。 第二采样器（148）由判决反馈均衡模式中的恢复的时钟信号和在芯片上的相位插值时钟信号触发。 还公开了其它实施例和特征。

公开(公告)号：EP2624511B1

公开(公告)日：2020-02-26

申请号：EP13150806.1

申请日：2013-01-10

申请人： Altera Corporation

发明人： Ding, Weiqi ,  Shumarayev, Sergey ,  Li, Peng ,  Shimanouchi, Masashi ,  Pan, Mingde

IPC分类号： H04L25/49 ,  H04L27/06 ,  H03D1/00 ,  H04L25/06

公开(公告)号：EP2814216A3

公开(公告)日：2015-02-11

申请号：EP14169882.9

申请日：2014-05-26

申请人： Altera Corporation

发明人： Wang, Bonnie I. ,  Ding, Weiqi ,  Hoang, Tim Tri ,  Hernandez, Richard ,  Lin, Haidang

IPC分类号： H04L25/02 ,  H03K19/0185

CPC分类号： H03F3/45071 ,  H03K19/018514 ,  H03K19/018585 ,  H04L25/0272

摘要： A voltage-mode differential driver (105) is disclosed. The differential driver (105) includes two driver arms (110-P, 110-N), each driver arm (110-P, 110-N) including a variable-impedance driver (116) for driving a single-ended output signal. Each variable-impedance driver (116) comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.

摘要翻译： 公开了一种电压模式差分驱动器（105）。 差分驱动器（105）包括两个驱动臂（110-P，110-N），每个驱动臂（110-P，110-N）包括用于驱动单端输出信号的可变阻抗驱动器（116）。 每个可变阻抗驱动器（116）包括多个驱动器片，其中每个驱动器片包括预驱动器电路和驱动器电路。 有利地，已经确定所公开的电压模式驱动器设计需要比常规电流模式驱动器更少的功率。 在一个实现中，所公开的电压模式驱动器设计提供独立编程两个单端输出的延迟以补偿差分偏斜的能力。 其他实施例和特征也被公开。

公开(公告)号：EP2733897A3

公开(公告)日：2016-02-10

申请号：EP13191034.1

申请日：2013-10-31

申请人： Altera Corporation

发明人： Ding, Weiqi ,  Shumarayev, Sergey ,  Li, Wei

IPC分类号： H04L25/03 ,  H04L25/02 ,  H04L25/14 ,  H04L27/01

CPC分类号： H04L25/0274 ,  H04L25/03885 ,  H04L25/14

摘要： Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter (110P) and a second variable-delay filter (110N), respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is generated based on the skew-indication signal, and the delay control signal is sent to at least one of the first and second variable-delay filters (110P, 110N). Other embodiments and features are also disclosed.

摘要翻译： 公开了用于自适应接收机延迟均衡的装置和方法。 一个实施例涉及一种用于自适应接收机延迟均衡的方法。 滤波的正极性和负极性信号分别由第一可变延迟滤波器（110P）和第二可变延迟滤波器（110N）产生。 在滤波的正极性和负极性信号之间确定延迟差，并且基于延迟差产生偏斜指示信号。 基于偏斜指示信号产生延迟控制信号，延迟控制信号被发送到第一和第二可变延迟滤波器（110P，110N）中的至少一个。 还公开了其它实施例和特征。

公开(公告)号：EP2590374A3

公开(公告)日：2014-10-01

申请号：EP12188984.4

申请日：2012-10-18

申请人： Altera Corporation

发明人： Ding, Weiqi ,  Shumarayev, Sergey ,  Li, Peng ,  Narayan, Sriram

IPC分类号： H04L25/03

CPC分类号： H04L25/03038 ,  H04L25/03146 ,  H04L2025/03573

摘要： One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit (210). The first signal path includes first equalization circuitry (204, 206), and the second signal path includes second equalization circuitry (208-1 to 208-N). The path selector circuit (210) is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

公开(公告)号：EP2387187A2

公开(公告)日：2011-11-16

申请号：EP11164954.7

申请日：2011-05-05

申请人： Altera Corporation

发明人： Ding, Weiqi

IPC分类号： H04L25/02

CPC分类号： H04L25/0286

摘要： Pre-emphasis may be able to operate in either of two modes. In a first mode, when one bit has a same value as the bit that immediately preceded it, an output signal for said one bit is based on a first electrical current reduced by a second electrical current. Otherwise the output signal for said one bit is based on the first current without regard for the second current. The second mode may be similar to the first mode when said one bit has the same value as the immediately preceding bit; but otherwise the output signal for said one bit is based on the first current increased by the second current. As an alternative to using the immediately preceding bit (as in the above "post-tap" operation), the immediately succeeding (following) bit may be used in generally the same way (in so-called "pre-tap" operation).

摘要翻译： 预加重可能能够以两种模式中的任一种运行。 在第一模式中，当一位与其之前的位具有相同的值时，所述一位的输出信号基于由第二电流减小的第一电流。 否则，所述一位的输出信号基于第一电流而不考虑第二电流。 当所述一个比特具有与前一比特相同的值时，第二模式可以类似于第一模式; 否则所述一位的输出信号基于第二电流增加的第一电流。 作为使用紧接在前的位（如在上述“后抽头”操作中）的替代方案，可以通常以相同的方式（在所谓的“预抽头”操作）中使用紧随其后的（后续）位。

公开(公告)号：EP2863598B1

公开(公告)日：2019-04-17

申请号：EP14188449.4

申请日：2014-10-10

申请人： Altera Corporation

发明人： Ding, Weiqi ,  Li, Wei

IPC分类号： H04L25/03 ,  H04L25/06

公开(公告)号：EP2833552A3

公开(公告)日：2015-02-18

申请号：EP14177855.5

申请日：2014-07-21

申请人： Altera Corporation

发明人： Ke, Yanjing ,  Tran, Thungoc M. ,  Ding, Weiqi ,  Shen, Jie ,  Liu, Xiong ,  Raman, Sangeeta ,  Li, Peng

IPC分类号： H03L7/00 ,  H04L7/033

CPC分类号： H04L25/03057 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L2025/03356

摘要： One embodiment relates to a receiver (100) with both decision feedback equalization and on-die instrumentation. A clock data recovery loop (122, 123, 124) obtains a recovered clock signal from an input signal, and a first sampler (126), which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator (134) receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler (148) is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

公开(公告)号：EP2814216A2

公开(公告)日：2014-12-17

申请号：EP14169882.9

申请日：2014-05-26

申请人： Altera Corporation

发明人： Wang, Bonnie I. ,  Ding, Weiqi ,  Hoang, Tim Tri ,  Hernandez, Richard ,  Lin, Haidang

IPC分类号： H04L25/02

CPC分类号： H03F3/45071 ,  H03K19/018514 ,  H03K19/018585 ,  H04L25/0272

摘要： A voltage-mode differential driver (105) is disclosed. The differential driver (105) includes two driver arms (110-P, 110-N), each driver arm (110-P, 110-N) including a variable-impedance driver (116) for driving a single-ended output signal. Each variable-impedance driver (116) comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.

摘要翻译： 公开了电压模式差分驱动器（105）。 差分驱动器（105）包括两个驱动器臂（110-P，110-N），每个驱动臂（110-P，110-N）包括用于驱动单端输出信号的可变阻抗驱动器（116）。 每个可变阻抗驱动器（116）包括多个驱动器片，其中每个驱动器片包括预驱动器电路和驱动器电路。 有利地，已经确定所公开的电压模式驱动器设计比常规电流模式驱动器需要更少的功率。 在一个实现中，所公开的电压模式驱动器设计提供了独立编程两个单端输出的延迟的能力，以补偿差分偏移。 还公开了其它实施例和特征。

公开(公告)号：EP2733897B1

公开(公告)日：2018-06-20

申请号：EP13191034.1

申请日：2013-10-31

申请人： Altera Corporation

发明人： Ding, Weiqi ,  Shumarayev, Sergey ,  Li, Wei

IPC分类号： H04L25/03 ,  H04L25/02 ,  H04L25/14 ,  H04L27/01

CPC分类号： H04L25/0274 ,  H04L25/03885 ,  H04L25/14

摘要： Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter (110P) and a second variable-delay filter (110N), respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is generated based on the skew-indication signal, and the delay control signal is sent to at least one of the first and second variable-delay filters (110P, 110N). Other embodiments and features are also disclosed.