发明公开
EP3041136A1 SEMICONDUCTOR DEVICE AND METHOD FOR ACCURATE CLOCK DOMAIN SYNCHRONIZATION OVER A WIDE FREQUENCY RANGE
审中-公开
半导体部件和方法精确的时钟域同步大面积FREQUENCY
- 专利标题： SEMICONDUCTOR DEVICE AND METHOD FOR ACCURATE CLOCK DOMAIN SYNCHRONIZATION OVER A WIDE FREQUENCY RANGE
- 专利标题（中）： 半导体部件和方法精确的时钟域同步大面积FREQUENCY
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申请号： EP15200633.4申请日： 2015-12-17
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公开(公告)号： EP3041136A1公开(公告)日： 2016-07-06
- 发明人: Shivaram, Krishna , Vandel, Eric
- 申请人： Semtech Corporation
- 申请人地址： 200 Flynn Road Camarillo, CA 93012 US
- 专利权人： Semtech Corporation
- 当前专利权人： Semtech Corporation
- 当前专利权人地址： 200 Flynn Road Camarillo, CA 93012 US
- 代理机构： Grünecker Patent- und Rechtsanwälte PartG mbB
- 优先权： US201414588040 20141231
- 主分类号： H03K5/135
- IPC分类号： H03K5/135 ; H04L7/033 ; H03L7/081 ; H03L7/087 ; H03L7/089 ; H03L7/091 ; H03L7/07 ; H03L7/10 ; G06F1/04
摘要：
A clock synchronization circuit (fig. 4a) has a clock sync detector (fig. 4a: 182). A first variable delay circuit (fig. 4a: 172) is coupled to a first input (178) of the clock sync detector. A controller (fig. 4a: 184) is coupled to a digital output (208) of the clock sync detector and a control input (fig. 4a: 185) of the first variable delay circuit (fig. 4a: 172). A first clock signal (178) is coupled to the first variable delay circuit (fig. 4a: 172). A second clock signal (179) is coupled to a second input of the clock sync detector (179). The clock sync detector includes a first flip-flop (fig. 4c: 220, 222) and a first delay element (fig. 4c: 224, 226; 234, 236) coupled between the first variable delay circuit (fig. 4a: 172) and a data input of the first flip-flop (fig. 4c: 220). A second variable delay circuit (fig. 4a: 174) is coupled to a second input (179) of the clock sync detector. A multiplexer (190, 192) is coupled between the first variable delay circuit (fig. 4a: 172) and the first input (178) of the clock sync detector. An offset compensation (201) calibrates (signal 202) the clock sync detector.
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