发明公开
EP3050080A4 METHODS OF FORMING PARALLEL WIRES OF DIFFERENT METAL MATERIALS THROUGH DOUBLE PATTERNING AND FILL TECHNIQUES
审中-公开
用于平行导线从各种金属材料通过双重结构方式和灌装技术的制备
- 专利标题： METHODS OF FORMING PARALLEL WIRES OF DIFFERENT METAL MATERIALS THROUGH DOUBLE PATTERNING AND FILL TECHNIQUES
- 专利标题（中）： 用于平行导线从各种金属材料通过双重结构方式和灌装技术的制备
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申请号： EP14847829申请日： 2014-09-25
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公开(公告)号： EP3050080A4公开(公告)日： 2017-06-14
- 发明人: CLARKE JAMES S , SCHMITZ ANTHONY C , SCHENKER RICHARD E
- 申请人： INTEL CORP
- 专利权人： INTEL CORP
- 当前专利权人： INTEL CORP
- 优先权： US201314040191 2013-09-27
- 主分类号： H01L21/768
- IPC分类号： H01L21/768 ; H01L23/532
摘要：
An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.
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