公开(公告)号：EP3238065A4

公开(公告)日：2018-08-01

申请号：EP14908661

申请日：2014-12-22

Applicant: INTEL CORP

Inventor： MAO CHENG

IPC: G06F11/22 ,  G06F11/27

CPC classification number: G01R31/31701 ,  G01R31/31705 ,  G01R31/31727 ,  G01R31/3177 ,  G06F9/3887 ,  G06F11/2236 ,  G06F11/27 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/4027 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/68 ,  G06F2213/0026

Abstract: A processor includes logic to implement a reconfigurable test access port with finite state machine control. A plurality of test access ports may each include a finite state machine for enabling implementation of different test interfaces to the processor, including JTAG IEEE 1149.1, JTAG IEEE 1149.7, and serial wire debug.

公开(公告)号：EP3234740A4

公开(公告)日：2018-08-01

申请号：EP15870673

申请日：2015-12-03

Applicant: INTEL CORP

Inventor： KAMHI GILA ,  FERENS RON ,  COOPERMAN VLADIMIR VOVA ,  NISTEL KOBI ,  HURWITZ BARAK

IPC: G06F3/01 ,  G06F3/14

CPC classification number: G09G5/003 ,  G06F3/14 ,  G06F9/542 ,  G06T19/006 ,  G09G2354/00 ,  G09G2358/00 ,  G09G2370/10

Abstract: Disclosed in some examples are methods systems and machine readable mediums in which actions or states of a first user (e.g., natural interactions) having a first corresponding computing device are observed by a sensor on a second computing device corresponding to a second user. A notification describing the observed actions or states of a first user may be shared across a network with the first corresponding computing device. In this way, the first computing device may be provided with information concerning the state of the user without having to directly sense the user.

公开(公告)号：EP3231177A4

公开(公告)日：2018-08-01

申请号：EP15867700

申请日：2015-11-06

Applicant: INTEL CORP

Inventor： LEI ZHIJUN ,  TANNER JASON

IPC: H04N19/119 ,  H04N19/122 ,  H04N19/14 ,  H04N19/176 ,  H04N19/192 ,  H04N19/96

CPC classification number: H04N19/176 ,  H04N19/119 ,  H04N19/122 ,  H04N19/14 ,  H04N19/192 ,  H04N19/96

Abstract: Techniques related to determining partition modes and transform sizes for video coding are discussed. Such techniques may include determining a portion of a video frame is flat and bypassing an inter-prediction partition check and/or a transform size check for the portion of the video frame based on the portion of the video frame being flat.

公开(公告)号：EP3230732A4

公开(公告)日：2018-08-01

申请号：EP15867660

申请日：2015-11-10

Applicant: INTEL CORP

Inventor： GULLBRAND JESSICA ,  COWAN MELISSA A ,  PAWASHE CHYTRA ,  EID FERAS

IPC: G08B21/12 ,  B05B17/00 ,  G01H13/00 ,  G01N1/22 ,  G01N21/17 ,  G01N33/00

CPC classification number: G08B21/182 ,  F15D1/0095 ,  G01N1/2273 ,  G01N1/24 ,  G01N2001/242 ,  G08B21/12 ,  G08B25/08 ,  H01L23/4735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for using synthetic jet technology as an air delivery device for sensing applications. In particular, a synthetic jet device is used to deliver a controlled airflow or other fluidic flow to a sensor measurement area. Such a sensing system can be used to detect accurate concentration of target features present in the ambient surroundings, such as gases, particles, solutions, mixtures, and any other environmental features that can be sensed from a controlled airflow. An example application is air quality monitoring by using one or more synthetic jet devices to deliver a known or otherwise controlled airflow to a sensing area, thereby allowing for detection of harmful or otherwise unacceptable concentrations of particulate matter, gases, or air pollutants. In some embodiments, a synthetic jet device is operatively coupled with a sensor via a flow channel in a common housing, so as to provide a controlled flow sensing system.

公开(公告)号：EP3238395A4

公开(公告)日：2018-07-25

申请号：EP14909254

申请日：2014-12-24

Applicant: INTEL CORP

Inventor： CHENG ALBERT S ,  LOVETT THOMAS D ,  PARKER MICHAEL A ,  HOOVER STEVEN F

IPC: H04L12/937 ,  H04L12/861 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935

CPC classification number: H04L49/3036 ,  H04L12/6418 ,  H04L49/101 ,  H04L49/103 ,  H04L49/254 ,  H04L49/505

Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.

公开(公告)号：EP3238006A4

公开(公告)日：2018-07-25

申请号：EP15874157

申请日：2015-12-17

Applicant: INTEL CORP

Inventor： KANDULA PHANI KUMAR ,  NATARAJAN NARAYANAN ,  THOMAS TESSIL ,  VENKATARAMAN SRIKRISHNAN

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a plurality of processing cores; a plurality of integrated voltage regulators (IVRs), and voltage regulator logic. Each IVR may be uniquely associated with one of the plurality of processing cores and comprising a plurality of bridge transistors. The voltage regulator logic may be to: monitor power state information of the core; determine, based on the power state information, whether the core has transitioned from a first power state to a second power state; and in response to a determination that the core has transitioned from the first power state to the second power state, adjust at least one of a bridge activation level of the IVR and a switching frequency of the IVR based at least on the second power state. Other embodiments are described and claimed.

公开(公告)号：EP3236839A4

公开(公告)日：2018-07-25

申请号：EP15873881

申请日：2015-10-12

Applicant: INTEL CORP

Inventor： SOMANATH GOWRI ,  NATARAJAN KARTHIK

IPC: A61B5/00 ,  A61B5/01 ,  A61B5/024 ,  A61B5/0404 ,  A61B5/053 ,  A61B5/11 ,  G08B21/04 ,  G16H40/00

CPC classification number: A61B5/747 ,  A61B5/0022 ,  A61B5/01 ,  A61B5/02438 ,  A61B5/0404 ,  A61B5/0533 ,  A61B5/1117 ,  A61B5/1118 ,  A61B5/4094 ,  A61B5/411 ,  A61B5/6804 ,  A61B5/6831 ,  A61B5/7264 ,  A61B5/7282 ,  A61B5/746 ,  A61B2560/0252 ,  A61B2562/0219 ,  G05B1/01 ,  G06F19/00 ,  G08B21/0423 ,  G08B21/0446 ,  G08B21/0453 ,  G08B21/0476 ,  G08B25/08 ,  G16H40/67

Abstract: An apparatus, method, and machine-readable medium for health monitoring and response are described herein. The apparatus includes a processor and a number of sensors configured to collect data corresponding to a user of the device. The apparatus also includes a health monitoring and response application, at least partially including hardware logic. The hardware logic of the health monitoring and response application is to test the data collected by any of the sensors to match the collected data with a predetermined health condition, determine a current health condition of the user based on the predetermined health condition that matches the collected data, and automatically perform an action based on the current health condition of the user.

公开(公告)号：EP3221996A4

公开(公告)日：2018-07-25

申请号：EP15860419

申请日：2015-11-17

Applicant: INTEL CORP

Inventor： SCHULZ STEFFEN ,  SCHUNTER MATTHIAS

IPC: H04L9/06 ,  G06F21/57 ,  H04L9/08 ,  H04L9/32 ,  H04L29/06

CPC classification number: H04L9/3236 ,  G06F21/57 ,  H04L9/0822 ,  H04L9/0866 ,  H04L9/3226 ,  H04L63/123

Abstract: The present disclosure is directed to sealing data using chain of trust key derivation. In at least one embodiment, a chain of trust may be used to derive sealing keys for sealing data on a device. The device may comprise, for example, at least a memory and processor. The processor may be to at least load code modules from the memory. Following the loading of a code module, the processor may further be to measure the code module, determine a sealing key corresponding to the code module, wherein the sealing key is determined based at least on a prior sealing key corresponding to a previously loaded code module and the measurement of the code module, and seal data corresponding to the loaded code module using the sealing key. Since the sealing keys are state dependent, a method for authorized migration of sealed data during software upgrades is also disclosed.

公开(公告)号：EP3238046A4

公开(公告)日：2018-07-18

申请号：EP15873974

申请日：2015-11-23

Applicant: INTEL CORP

Inventor： LAI PATRICK P ,  SONDAG TYLER N ,  WINKEL SEBASTIAN ,  XEKALAKIS POLYCHRONIS ,  SCHUCHMAN ETHAN

IPC: G06F9/38 ,  G06F7/57 ,  G06F9/30

CPC classification number: G06F9/455 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30058 ,  G06F9/3017

Abstract: In one embodiment a binary translation is used to fuse multiple macroinstructions of an instruction set architecture into a single macroinstruction. Fusible instruction sequences include a sequence of increment, compare, and jump instructions. In one embodiment, a processing device provides support for the fused macroinstruction. In one embodiment, the processing device executes the fused macroinstruction within a single execution stage of a processor pipeline. In one embodiment, the fused macroinstruction is performed within a single execution cycle.

公开(公告)号：EP3238004A4

公开(公告)日：2018-07-18

申请号：EP15874067

申请日：2015-11-30

Applicant: INTEL CORP

Inventor： ROYCHOWDHURY AROJIT ,  SETHURAMAN RAMANATHAN ,  DURG AJAYA V ,  UGHREJA RAKESH A

IPC: G06F1/32 ,  G06F1/26 ,  G06F15/78 ,  G11C5/14

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3296 ,  G06F15/781 ,  G11C5/148 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.