Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit utilizing a decision feedback equalization (DFE) circuit. The CDR circuit is to output a recovered clock signal. During the operation of the phase adjustment circuit the CDR utilizes the DFE circuit to determine a locking position of the recovered clock signal.