公开(公告)号：EP3353562A1

公开(公告)日：2018-08-01

申请号：EP16849260.1

申请日：2016-08-24

申请人： Intel Corporation

发明人： XU, Mingming ,  GIACONI, Stefano ,  WANG, Wei

IPC分类号： G01R31/317 ,  G01R13/02

CPC分类号： G06K9/0053 ,  G01R13/02 ,  G06K9/00503 ,  G06K9/00557 ,  G06K9/00604

摘要： Some embodiments include apparatuses and methods having a receiver unit included in a die and a measurement unit included in the die. The receiver unit includes a sampler to sample a first signal based on timing of a first clock signal to generate a second signal. The measurement unit is arranged to sample the first signal based on timing of a second clock signal to provide information for generation of a graph presenting an eye scan of the first signal. The second clock signal has a frequency asynchronous with a frequency of the first clock signal.

公开(公告)号：EP3087697B1

公开(公告)日：2020-04-01

申请号：EP14875758.6

申请日：2014-11-21

申请人： Intel Corporation

发明人： GIACONI, Stefano ,  XU, Mingming

IPC分类号： H04L7/033 ,  H04L25/03 ,  H04L7/00

公开(公告)号：EP3087697A1

公开(公告)日：2016-11-02

申请号：EP14875758.6

申请日：2014-11-21

申请人： Intel Corporation

发明人： GIACONI, Stefano ,  XU, Mingming

IPC分类号： H04L7/033

摘要： Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit utilizing a decision feedback equalization (DFE) circuit. The CDR circuit is to output a recovered clock signal. During the operation of the phase adjustment circuit the CDR utilizes the DFE circuit to determine a locking position of the recovered clock signal.