发明公开
EP3117462A1 HIGH DENSITY SRAM ARRAY DESIGN WITH WORD LINE LANDING PADS EXTENDING OVER THE CELL BOUNDARY IN THE ROW DIRECTION
审中-公开
KONSTRUKTION EINER HOCHDICHTEN SRAM-ARRAY MIT WORTZEILENLANDEPADS，DIEÜBERDIE ZELLENBEGRENZUNG在REIHENRICHTUNG HINAUSGEHEN
- 专利标题： HIGH DENSITY SRAM ARRAY DESIGN WITH WORD LINE LANDING PADS EXTENDING OVER THE CELL BOUNDARY IN THE ROW DIRECTION
- 专利标题（中）： KONSTRUKTION EINER HOCHDICHTEN SRAM-ARRAY MIT WORTZEILENLANDEPADS，DIEÜBERDIE ZELLENBEGRENZUNG在REIHENRICHTUNG HINAUSGEHEN
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申请号： EP15715628.2申请日： 2015-03-30
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公开(公告)号： EP3117462A1公开(公告)日： 2017-01-18
- 发明人: MOJUMDER, Niladri Narayan , WANG, Zhongze , SONG, Stanley Seungchul , YEAP, Choh Fei
- 申请人： Qualcomm Incorporated
- 申请人地址： 5775 Morehouse Drive San Diego, CA 92121-1714 US
- 专利权人： Qualcomm Incorporated
- 当前专利权人： Qualcomm Incorporated
- 当前专利权人地址： 5775 Morehouse Drive San Diego, CA 92121-1714 US
- 代理机构： Dunlop, Hugh Christopher
- 优先权： US201414274378 20140509
- 国际公布： WO2015171217 20151112
- 主分类号： H01L27/11
- IPC分类号： H01L27/11 ; H01L27/02
摘要：
A static random access memory (SRAM) cell (340) includes a first conductive layer (M1) including a wordline landing pad (320) extending into a neighboring memory cell (360) in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline (WL1) coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via (Via0) coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer and a second via (Via1) coupling the wordline landing pad and the wordline of the second conductive layer.
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