公开(公告)号：EP4214750A1

公开(公告)日：2023-07-26

申请号：EP21758907.6

申请日：2021-07-30

申请人： QUALCOMM INCORPORATED

发明人： SONG, Stanley Seungchul ,  SHARMA, Deepak ,  CHAVA, Bharani ,  LIM, Hyeokjin ,  FENG, Peijie ,  KANG, Seung Hyuk ,  KIM, Jonghae ,  CHIDAMBARAM, Periannan ,  RIM, Kern ,  NALLAPATI, Giridhar ,  BOYNAPALLI, Venugopal ,  VANG, Foua

IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L23/48

公开(公告)号：EP3397589B1

公开(公告)日：2019-11-27

申请号：EP16791267.4

申请日：2016-10-27

申请人： Qualcomm Incorporated

发明人： BADAROGLU, Mustafa ,  MACHKAOUTSAN, Vladimir ,  SONG, Stanley Seungchul ,  XU, Jeffrey Junhao ,  NOWAK, Matthew Michael ,  YEAP, Choh Fei

IPC分类号： H01L29/775 ,  H01L29/08 ,  H01L29/423 ,  B82Y10/00 ,  H01L21/336

公开(公告)号：EP3198607B1

公开(公告)日：2018-12-26

申请号：EP15772122.6

申请日：2015-09-15

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： G11C11/419 ,  G11C11/412

CPC分类号： G11C11/419 ,  G11C11/412

摘要： Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

公开(公告)号：EP3311225A1

公开(公告)日：2018-04-25

申请号：EP16732178.5

申请日：2016-06-15

申请人： Qualcomm Incorporated

发明人： CHEN, Xiangdong ,  LIM, Hyeokjin Bruce ,  KWON, Ohsang ,  MALABRY, Mickael ,  ZHANG, Jingwei ,  STEPHANY, Raymond George ,  YANG, Haining ,  RIM, Kern ,  SONG, Stanley Seungchul ,  GUPTA, Mukul ,  VANG, Foua

IPC分类号： G03F7/20 ,  G03F1/00 ,  G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

摘要： In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

公开(公告)号：EP3262682A1

公开(公告)日：2018-01-03

申请号：EP16703005.5

申请日：2016-01-11

申请人： Qualcomm Incorporated

发明人： MACHKAOUTSAN, Valdimir ,  BADAROGLU, Mustafa ,  XU, Jeffrey Junhao ,  SONG, Stanley Seungchul ,  YEAP, Choh Fei

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00

CPC分类号： H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

摘要： An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

公开(公告)号：EP2973577B1

公开(公告)日：2017-12-20

申请号：EP14722821.7

申请日：2014-03-11

申请人： Qualcomm Incorporated

发明人： SONG, Stanley Seungchul ,  WANG, Zhongze

IPC分类号： G11C11/417 ,  G11C11/413 ,  G11C7/04 ,  G11C5/14 ,  G06F17/50

CPC分类号： G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

公开(公告)号：EP3198607A1

公开(公告)日：2017-08-02

申请号：EP15772122.6

申请日：2015-09-15

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： G11C11/412

CPC分类号： G11C11/419 ,  G11C11/412

摘要： Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

摘要翻译： 系统和方法涉及包括具有第一上拉晶体管，第一下拉晶体管和第一存储节点的第一反相器的第七晶体管静态随机存取存储器（7T SRAM）位单元，以及具有第一反相器 第二上拉晶体管，第二下拉晶体管和第二存储节点。 第二存储节点耦合到第一上拉晶体管和第一下拉晶体管的栅极。 传输门被配置为在写入操作，待机模式和保持模式期间选择性地将第一存储节点耦合到第二上拉晶体管和第二下拉晶体管的栅极，并且选择性地将第一存储节点从 在读取操作期间第一上拉晶体管和第一下拉晶体管的栅极。 7T SRAM位单元可以通过耦合到第一存储节点的存取晶体管读取或写入。

公开(公告)号：EP4360131A1

公开(公告)日：2024-05-01

申请号：EP22741028.9

申请日：2022-05-23

申请人： QUALCOMM INCORPORATED

发明人： CHAVA, Bharani ,  ROY, Abinash ,  SONG, Stanley Seungchul ,  KIM, Jonghae

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/5385 ,  H01L23/5383 ,  H01L23/49816 ,  H01L21/4857 ,  H01L25/0655 ,  H01L25/0652 ,  H01L2225/0651720130101 ,  H01L2225/0651320130101 ,  H01L2225/105820130101 ,  H01L25/105 ,  H01L25/50 ,  H01L24/16

公开(公告)号：EP4161868A1

公开(公告)日：2023-04-12

申请号：EP21726501.6

申请日：2021-04-28

申请人： QUALCOMM INCORPORATED

发明人： YUAN, Jun ,  FENG, Peijie ,  SONG, Stanley Seungchul ,  RIM, Kern

IPC分类号： B82Y10/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423

公开(公告)号：EP3278365A1

公开(公告)日：2018-02-07

申请号：EP16705652.2

申请日：2016-02-03

申请人： Qualcomm Incorporated

发明人： SONG, Stanley Seungchul ,  XU, Jeffrey Junhao ,  RIM, Kern ,  YANG, Da ,  ZHU, John Jianhong ,  BAO, Junjing ,  MOJUMDER, Niladri Narayan ,  MACHKAOUTSAN, Vladimir ,  BADAROGLU, Mustafa ,  YEAP, Choh Fei

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764

CPC分类号： H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.