发明公开
EP3238031A1 INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD
审中-公开
用于执行矢量饱和双字/四字添加的指令和逻辑
- 专利标题： INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD
- 专利标题（中）： 用于执行矢量饱和双字/四字添加的指令和逻辑
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申请号： EP15873977.1申请日： 2015-11-23
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公开(公告)号： EP3238031A1公开(公告)日： 2017-11-01
- 发明人: OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , TOLL, Bret L. , CORBAL SAN ADRIAN, Jesus , CHARNEY, Mark J. , GIRKAR, Milind B.
- 申请人： Intel Corporation
- 申请人地址： 2200 Mission College Boulevard Santa Clara, CA 95054 US
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： 2200 Mission College Boulevard Santa Clara, CA 95054 US
- 代理机构： Samson & Partner Patentanwälte mbB
- 优先权： US201414582007 20141223
- 国际公布： WO2016105771 20160630
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F7/485
摘要：
In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.
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