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    TENSOR CALCULATION UNIT AND USE METHOD, AND DATA PROCESSING APPARATUS AND OPERATION METHOD
    1.
    发明公开
    TENSOR CALCULATION UNIT AND USE METHOD, AND DATA PROCESSING APPARATUS AND OPERATION METHOD 审中-公开

    公开(公告)号：EP4446870A1

    公开(公告)日：2024-10-16

    申请号：EP23892911.1

    申请日：2023-03-06

    申请人： Hygon Information Technology Co., Ltd.

    发明人： ZUO, Hang

    IPC分类号： G06F7/485

    摘要： A tensor calculation unit and a use method, and a data processing apparatus and an operation method. The tensor calculation unit comprises a first multiply-add operator and a second multiply-add operator, which are cascaded, wherein the first multiply-add operator comprises a first input port, a second input port, a third input port and a first output port, the first input port, the second input port and the third input port are used for respectively receiving parameters A0, B0 and C, and the first multiply-add operator is configured to perform the calculation of D0 = A0 × B0 +C, and output a calculation result D0 at the first output port; and the second multiply-add operator comprises a fourth input port, a fifth input port, a sixth input port and a second output port, the fourth input port and the fifth input port are used for respectively receiving parameters A1 and B1, the sixth input port is coupled to the first output port so as to receive the calculation result D0, and the second multiply-add operator is configured to perform the calculation of D1 = A1 × B1 + D0, and output a calculation result D1 at the second output port. The tensor calculation unit can be infinitely extended and stacked.

    METHOD AND SYSTEM FOR PROCESSING FLOATING POINT NUMBERS
    5.
    发明公开
    METHOD AND SYSTEM FOR PROCESSING FLOATING POINT NUMBERS 审中-公开

    公开(公告)号：EP3958113A1

    公开(公告)日：2022-02-23

    申请号：EP21190433.9

    申请日：2021-08-09

    申请人： Imagination Technologies Limited

    发明人： Ferrere, Thomas

    IPC分类号： G06F7/485 ,  G06F7/509

    摘要： A method and system for processing a set of 'k' floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (m i ) and an exponent (e i ). The method comprises receiving the set of 'k' floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (m i ) with a bit-length of 'b' bits. The method further comprises creating a set of 'k' numbers (y i ) based on the mantissas of the 'k' floating-point numbers, the numbers having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length 'b' of the mantissa (m i ). The method includes identifying a maximum exponent (e max ) among the exponents e i , aligning the magnitude bits of the numbers (y i ) based on the maximum exponent (e max ) and processing the set of 'k' numbers concurrently.

    APPARATUS AND METHOD FOR FUSED ADD-ADD INSTRUCTIONS
    7.
    发明公开
    APPARATUS AND METHOD FOR FUSED ADD-ADD INSTRUCTIONS 审中-公开
    装置和方法用于保存加法指令

    公开(公告)号：EP3238033A1

    公开(公告)日：2017-11-01

    申请号：EP15874009.2

    申请日：2015-11-24

    申请人： Intel Corporation

    发明人： CORBAL SAN ADRIAN, Jesus ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  OULD-AHMED-VALL, Elmoustapha ,  ESPASA, Roger ,  SOLE, Guillem ,  FERNANDEZ, Manel ,  HICKMANN, Brian J.

    IPC分类号： G06F9/30 ,  G06F7/485

    CPC分类号： G06F9/30196 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/30185

    摘要： In one embodiment of the invention, a processor including a storage location configured to store a set of source packed-data operands, each of the operands having a plurality of packed-data elements that are positive or negative according to an immediate bit value within one of the operands. The processor also including: a decoder to decode an instruction requiring an input of a plurality of source operands, and an execution unit to receive the decoded instructions and to generate a result that is a sum of the source operands. In one embodiment, the result is stored back into one of the source operands or the result is stored into an operand that is independent of the source operands.

    摘要翻译： 在本发明的一个实施例中，包括存储位置的处理器被配置为存储一组源打包数据操作数，每个操作数具有多个打包数据元素，所述多个打包数据元素根据一个位内的直接位值为正或负 的操作数。 该处理器还包括：解码器，用于解码需要输入多个源操作数的指令;以及执行单元，用于接收解码的指令并生成作为源操作数之和的结果。 在一个实施例中，结果被存储回源操作数中的一个，或者结果被存储到独立于源操作数的操作数中。

    Floating-point adder circuitry
    8.
    发明公开
    Floating-point adder circuitry 有权
    Gleitkomma-Addierer-Schaltung

    公开(公告)号：EP2846257A1

    公开(公告)日：2015-03-11

    申请号：EP14182740.2

    申请日：2014-08-29

    申请人： Altera Corporation

    发明人： Czajkowski, Tomasz

    IPC分类号： G06F7/485 ,  G06F7/499

    CPC分类号： G06F7/485 ,  G06F5/012 ,  G06F7/49915 ,  G06F17/10 ,  G06F2207/483

    摘要： An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.

    摘要翻译： 提供一种集成电路，其执行涉及至少三个浮点数的浮点加法或减法运算。 通过动态扩展尾数位数，以最大指数确定浮点数，并将其他浮点数的尾数向右移动，对浮点数进行预处理。 每个扩展尾数具有进入浮点运算的尾数的位数的至少两倍。 精确的位扩展取决于要添加的浮点数的数量。 指数小于最大指数的所有浮点数的尾数向右移动。 右移位的数量取决于最大指数和相应浮点指数之间的差异。