发明公开
EP3261115A1 CHIP SCALE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
审中-公开
芯片尺寸半导体封装及其制造方法
- 专利标题： CHIP SCALE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- 专利标题（中）： 芯片尺寸半导体封装及其制造方法
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申请号： EP16175983.2申请日： 2016-06-23
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公开(公告)号： EP3261115A1公开(公告)日： 2017-12-27
- 发明人: GROENHUIS, Roelf , VAN GEMERT, Leo , KAMPHUIS, Tonny , GULPEN, Jan
- 申请人： NXP B.V.
- 申请人地址： High Tech Campus 60 5656 AG Eindhoven NL
- 专利权人： NXP B.V.
- 当前专利权人： NXP B.V.
- 当前专利权人地址： High Tech Campus 60 5656 AG Eindhoven NL
- 代理机构： Hardingham, Christopher Mark
- 主分类号： H01L21/56
- IPC分类号： H01L21/56 ; H01L23/48 ; H01L23/31
摘要：
This disclosure relates to a method of forming a chip scale semiconductor package, the method comprising: providing a carrier (100) having a cavity (102) formed therein; forming electrical contacts (104) at a base portion and sidewalls portions of the cavity (102); placing a semiconductor die (110) in the base of the cavity (102); connecting bond pads of the semiconductor die (110) to the electrical contacts (104); encapsulating the semiconductor die (110); and removing the carrier (100) to expose the electrical contacts (104), such that the electrical contacts (104) are arranged directly on the encapsulation material (114).
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