发明公开
EP3269039A1 TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM
审中-公开
设置栅极过度偏置的晶体管及其电路
- 专利标题: TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM
- 专利标题(中): 设置栅极过度偏置的晶体管及其电路
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申请号: EP16708533.1申请日: 2016-02-12
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公开(公告)号: EP3269039A1公开(公告)日: 2018-01-17
- 发明人: LOKE, Alvin Leng Sun , YU, Bo , THILENIUS, Stephen Clifford , JALILIZEINALI, Reza , ISAKANIAN, Patrick
- 申请人: Qualcomm Incorporated
- 申请人地址: 5775 Morehouse Drive San Diego, CA 92121-1714 US
- 专利权人: Qualcomm Incorporated
- 当前专利权人: Qualcomm Incorporated
- 当前专利权人地址: 5775 Morehouse Drive San Diego, CA 92121-1714 US
- 代理机构: Schmidbauer, Andreas Konrad
- 优先权: US201562130951P 20150310; US201514812516 20150729
- 国际公布: WO2016144482 20160915
- 主分类号: H03K19/003
- IPC分类号: H03K19/003 ; H03K19/0185
摘要:
An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.
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