Method for controlling a plurality of memory devices comprising supplying a mode register command and a mode signal in common to the plurality of memory devices, supplying a first enable signal having a first logic level to a first memory device of the plurality of memory devices, the first enable signal being supplied with a predetermined latency after supplying the mode register command and the mode signal, and supplying a second enable signal having a second logic level to a second memory device of the plurality of memory devices, the second signal being supplied with the predetermined latency after supplying the mode register command and the mode signal. The mode register command is decoded and delayed by a latency shifter in each of the plurality of memory devices.