公开(公告)号：EP3401912A1

公开(公告)日：2018-11-14

申请号：EP18182031.7

申请日：2012-09-27

申请人： Longitude Semiconductor S.à.r.l.

发明人： KONDO, Chikara

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

摘要： Method for controlling a plurality of memory devices comprising supplying a mode register command and a mode signal in common to the plurality of memory devices, supplying a first enable signal having a first logic level to a first memory device of the plurality of memory devices, the first enable signal being supplied with a predetermined latency after supplying the mode register command and the mode signal, and supplying a second enable signal having a second logic level to a second memory device of the plurality of memory devices, the second signal being supplied with the predetermined latency after supplying the mode register command and the mode signal. The mode register command is decoded and delayed by a latency shifter in each of the plurality of memory devices.

公开(公告)号：EP3206209B1

公开(公告)日：2018-07-11

申请号：EP16206638.5

申请日：2012-09-27

申请人： Longitude Semiconductor S.à.r.l.

发明人： KONDO, Chikara

IPC分类号： G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4072 ,  G06F13/16

CPC分类号： G11C11/4093 ,  G06F13/161 ,  G11C7/1045 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/14

摘要： Disclosed herein is a semiconductor device that includes a command decoder activating a first mode register setting signal in response to a mode register setting command supplied from outside, a first latency shifter activating a second mode register setting signal after elapse of predetermined cycles of a clock signal since the first mode register setting signal is activated, and a mode register storing a mode signal supplied from outside in response to the second mode register setting signal.