A circuit (10) for use e.g. in digital-to-analog converters, comprises a first transistor (M1) and a second transistor (M3) having respective control terminals coupled to a first bias voltage node (VB1) and a second bias voltage node (VB2) as well as a first electronic switch (M2). The current paths through the first (M1) and second (M3) transistor and the first electronic switch (M2) are cascaded in an output current line between a circuit output node (Iout) and ground (GND). A second (M4) and a third (M5) electronic switch are provided activatable to a conductive state to provide charge transfer current paths coupling the charge transfer node (Y).