发明公开
- 专利标题: SEMICONDUCTOR DEVICE
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申请号: EP18809350.4申请日: 2018-04-12
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公开(公告)号: EP3633733A1公开(公告)日: 2020-04-08
- 发明人: MIYOSHI, Tomoyuki , MORI, Mutsuhiro , TAKEUCHI, Yujiro , FURUKAWA, Tomoyasu
- 申请人: Hitachi Power Semiconductor Device, Ltd.
- 申请人地址: 2-2 Omika-cho 5-chome Hitachi-shi, Ibaraki 319-1221 JP
- 专利权人: Hitachi Power Semiconductor Device, Ltd.
- 当前专利权人: Hitachi Power Semiconductor Device, Ltd.
- 当前专利权人地址: 2-2 Omika-cho 5-chome Hitachi-shi, Ibaraki 319-1221 JP
- 代理机构: Mewburn Ellis LLP
- 优先权: JP2017105575 20170529
- 国际公布: WO2018221032 20181206
- 主分类号: H01L29/739
- IPC分类号: H01L29/739 ; H01L29/12 ; H01L29/78
摘要:
Provided is an IGBT capable of achieving both low conduction loss and low switching loss in the IGBT and achieving low power consumption, and a power conversion device to which the IGBT is applied. The semiconductor device includes a first conductivity type semiconductor layer formed on a first main surface of a semiconductor substrate, a second conductivity type well region formed on the first main surface side and in contact with the first conductivity type semiconductor layer, a first gate electrode and a second gate electrode adjacent to each other across the second conductivity type well region and in contact with the first conductivity type semiconductor layer and the second conductivity type well region through a gate insulating film, a first conductivity type emitter region formed on the first main surface side of the second conductivity type well region, a second conductivity type power supply region that penetrates the first conductivity type emitter region and is electrically connected to the second conductivity type well region, an emitter electrode electrically connected to the second conductivity type well region through the second conductivity type power supply region, a second conductivity type collector layer formed on a second main surface side of the semiconductor substrate that is opposite to the first main surface side and in contact with the first conductivity type semiconductor layer, and a collector electrode electrically connected to the second conductivity type collector layer. An interval between the first gate electrode and the second gate electrode is narrower than an interval between the first gate electrode and another adjacent gate electrode and an interval between the second gate electrode and another adjacent gate electrode. Each of the first gate electrode and the second gate electrode is electrically connected to any of a switching gate wiring and a carrier control gate wiring. The number of gate electrodes connected to the carrier control gate wiring is larger than the number of gate electrodes connected to the switching gate wiring.
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