发明公开
- 专利标题: DIGITAL PHASE CONTROLLED PLLS
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申请号: EP20208818.3申请日: 2015-04-27
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公开(公告)号: EP3823170A1公开(公告)日: 2021-05-19
- 发明人: SJÖLAND, Henrik , EK, Staffan , PÅHLSSON, Tony
- 申请人: Telefonaktiebolaget LM Ericsson (publ)
- 申请人地址: SE 164 83 Stockholm
- 代理机构: Ericsson
- 主分类号: H03L7/197
- IPC分类号: H03L7/197 ; H03L7/081 ; H03L7/183 ; H04B7/06
摘要:
A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.
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