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    SINGLE VCO FREQUENCY SYNTHESIZER ARCHITECTURE FOR UWB APPLICATIONS
    2.
    发明公开
    SINGLE VCO FREQUENCY SYNTHESIZER ARCHITECTURE FOR UWB APPLICATIONS 审中-公开

    公开(公告)号：EP4439985A1

    公开(公告)日：2024-10-02

    申请号：EP24166614.8

    申请日：2024-03-27

    申请人： Qorvo US, Inc.

    发明人： BOUHAMAME, Mohamed

    IPC分类号： H03L7/183 ,  H03L7/197

    CPC分类号： H03L7/183 ,  H03L7/1976

    摘要： The present disclosure relates to a frequency synthesizer capable of generating a full spectrum for ultra-wideband applications by utilizing a single voltage-controlled oscillator (VCO). The disclosed frequency synthesizer includes a phase-frequency detector (PFD), a charge pump (CP), a VCO, a feedback divider, and a divider bank. The PFD, the CP, the VCO, and the feedback divider are coupled in series in a closed loop, while the divider bank follows the VCO and is not included in the closed loop. Herein, the VCO has a tuning range less than 35%. The divider bank includes two or more divider branches parallel to each other, each of which is configured to provide a different division ratio. An oscillating spectrum of the VCO and division ratios of the two or more divider branches are selected such that the divider bank is capable of providing a continuous spectrum with at least a 64% frequency coverage.

    DIGITAL PHASE CONTROLLED PLLS
    7.
    发明公开
    DIGITAL PHASE CONTROLLED PLLS 审中-公开

    公开(公告)号：EP3823170A1

    公开(公告)日：2021-05-19

    申请号：EP20208818.3

    申请日：2015-04-27

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： SJÖLAND, Henrik ,  EK, Staffan ,  PÅHLSSON, Tony

    IPC分类号： H03L7/197 ,  H03L7/081 ,  H03L7/183 ,  H04B7/06

    摘要： A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.