The present disclosure provides an apparatus comprising a package assembly comprising a plurality of chiplets and a plurality of interconnect structures. The plurality of chiplets including a first chiplet comprising a first base chiplet coupled to a bridge interconnect and an interconnect structure. The first base chiplet including an interconnect fabric, and a first plurality of level 3 cache banks to cache data read from and transmitted to a memory, a second chiplet comprising a second base chiplet, the second chiplet coupled to the first chiplet over the bridge interconnect; and a third chiplet including a second plurality of level 3 cache banks, the third chiplet stacked on the first base chiplet in a 3D arrangement and coupled to the first base chiplet over the interconnect structure.