In some example embodiments, there may be provided a multi-chip module accelerator usable to execute tensor data processing operations, the multi-chip module accelerator comprising a multi-chip module comprising a memory stack including multiple memory dies; and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry comprising multiprocessor cores to execute matrix multiplication and accumulate operations, wherein the matrix multiplication and accumulate operations comprise floating-point operations; the floating-point operations are configurable to comprise two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions; the floating-point operations comprise a first operation at a first precision and a second operation at a second precision; and the first operation comprises a multiply having at least one 16-bit floating-point input and the second operation comprises an accumulate having a 32-bit floating-point input. Related systems, non-transitory machine-readable storage medium, methods and articles of manufacture are also described.