A chip test circuit and a circuit test method are provided, which can be used to test a chip circuit in EDA software, and are used to resolve problems of winding congestion and complex test configuration in an existing test solution. The test circuit transmits input data of a test vector to a data distribution circuit (301) through an input of a test bus, and transmits the input data of the test vector to a scan input channel of a tested circuit (01) through the data distribution circuit (301). After scanning of the tested circuit (01) ends, output data of the test vector of the scan output channel of the tested circuit (01) is transmitted to an output of the test bus through the data distribution circuit (301) to complete the test of the tested circuit (01). A dynamic correspondence between the data distribution circuit (301) and the test bus (02) is implemented by configuring a first selector (302), so that test resources can be dynamically allocated. This can greatly optimize a winding congestion problem, reduce test costs, simplify a configuration process, and improve test efficiency.