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公开(公告)号：EP4198529A1
公开(公告)日：2023-06-21
申请号：EP20950892.8
申请日：2020-08-31
发明人： HUANG, Yu , CUI, Changming , HUANG, Junlin , FU, Haitao
IPC分类号： G01R31/3167
摘要： Embodiments of this application provide a test circuit (03) in a chip and a circuit test method, relate to the field of electronic technologies, and may be applied to EDA software, to resolve problems of winding congestion and complex test configuration in a current test solution. The test circuit (03) transmits input data of a test vector to a data distribution circuit (301) by using an input of a test bus (02), and transmits the input data of the test vector to a scan input channel in a circuit under test (01) by using the data distribution circuit (301). After scan of the circuit under test (01) is completed, output data of the test vector on a scan output channel in the circuit under test (01) is transmitted to an output of the test bus (02) by using the data distribution circuit (301), to complete testing of the circuit under test (01). A dynamic correspondence between the data distribution circuit (301) and the test bus (02) may be configured based on a specific test solution, so that a test resource can be dynamically allocated. In this way, the winding congestion problem can be optimized to a great extent, to reduce test costs, and a configuration process can be simplified to improve test efficiency.
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2.发明公开
公开(公告)号：EP4386396A1
公开(公告)日：2024-06-19
申请号：EP21957779.8
申请日：2021-09-23
发明人： CUI, Changming , FU, Haitao , ZHANG, Yu , DENG, Bin , HUANG, Junlin
IPC分类号： G01R31/28
CPC分类号： G01R31/28
摘要： This application relates to the field of integrated circuit testing, and discloses a test circuit, an integrated circuit, an electronic device, and a method for generating a test circuit, to implement consistency of timing of data transmission on a test bus and improve a transmission rate of the test bus. The test circuit includes a first input bus, a second input bus, a first output bus, a second output bus, a first dynamic routing unit DRU, and a first register. In a clock cycle: the first DRU outputs test excitation from the first input bus to a tested circuit, and outputs a test response from the tested circuit to the first output bus; or the first DRU outputs data from the first input bus to the first output bus; and the first register outputs data from the second input bus to the second output bus.
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公开(公告)号：EP4194865A1
公开(公告)日：2023-06-14
申请号：EP20950901.7
申请日：2020-08-31
发明人： CUI, Changming , HUANG, Junlin , HUANG, Yu , FU, Haitao
IPC分类号： G01R31/28
摘要： A chip test circuit and a circuit test method are provided, which can be used to test a chip circuit in EDA software, and are used to resolve problems of winding congestion and complex test configuration in an existing test solution. The test circuit transmits input data of a test vector to a data distribution circuit (301) through an input of a test bus, and transmits the input data of the test vector to a scan input channel of a tested circuit (01) through the data distribution circuit (301). After scanning of the tested circuit (01) ends, output data of the test vector of the scan output channel of the tested circuit (01) is transmitted to an output of the test bus through the data distribution circuit (301) to complete the test of the tested circuit (01). A dynamic correspondence between the data distribution circuit (301) and the test bus (02) is implemented by configuring a first selector (302), so that test resources can be dynamically allocated. This can greatly optimize a winding congestion problem, reduce test costs, simplify a configuration process, and improve test efficiency.
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