- 专利标题： A METHOD FOR FORMING A SEMICONDUCTOR DEVICE
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申请号： EP21215370.4申请日： 2021-12-17
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公开(公告)号： EP4199112A1公开(公告)日： 2023-06-21
- 发明人: CHAN, Boon Teik , VANDOOREN, Anne , RYCKAERT, Julien , HORIGUCHI, Naoto
- 申请人： IMEC VZW
- 申请人地址： BE 3001 Leuven Kapeldreef 75
- 代理机构： AWA Sweden AB
- 主分类号： H01L29/775
- IPC分类号： H01L29/775 ; H01L27/092 ; H01L21/336 ; H01L21/8238 ; H01L21/822 ; H01L29/423 ; H01L29/06 ; B82Y10/00
摘要：
The disclosure relates to a method for forming a semiconductor device, the method comprising:
forming a device layer stack on a substrate, the device layer stack comprising:
- a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and
- a second sub-stack on the first sub-stack and comprising a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer,
wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and
wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack.
The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.
forming a device layer stack on a substrate, the device layer stack comprising:
- a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and
- a second sub-stack on the first sub-stack and comprising a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer,
wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and
wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack.
The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.
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