公开(公告)号：EP4513542A1

公开(公告)日：2025-02-26

申请号：EP24163892.3

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： PARK, Jisoo ,  KANG, Byungju ,  LIM, Jaehyoung ,  CHUN, Kwanyoung ,  CHOI, Subin

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L29/417 ,  H01L29/775

Abstract: A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.

公开(公告)号：EP4510177A2

公开(公告)日：2025-02-19

申请号：EP24192367.1

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd

Inventor： PARK, Panjae ,  KIM, Jintae ,  SEO, Kang-ill

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/775

Abstract: An integrated circuit device includes a wimpy transistor stack (TSw_4) and a reference transistor stack (TS) on a substrate (100). The wimpy transistor stack (TSw_4) may include a first intergate insulator (305a) that is thicker than a second intergate insulator (t10) of the reference transistor stack (TS). Due to the thicker first intergate insulator 305a, a number of first upper channel regions (402a) of the wimpy transistor stack (TSw_4) may be less than a number of second upper channel regions (402b) of reference transistor stack (TS), and/or a number of first lower channel regions (202a) of the wimpy transistor stack (TSw_4) may be less than a number of second lower channel regions (202b) of the reference transistor stack (TS).

公开(公告)号：EP4505514A1

公开(公告)日：2025-02-12

申请号：EP23853184.2

申请日：2023-06-12

Applicant: SanDisk Technologies LLC

Inventor： MATSUNO, Koichi

IPC: H01L21/822 ,  H01L21/77 ,  H01L21/82 ,  H01L21/8232

公开(公告)号：EP4495986A1

公开(公告)日：2025-01-22

申请号：EP24188865.0

申请日：2024-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUN, Seungchan ,  BAEK, Jaejik ,  SEO, Kang-ill

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

Abstract: Provided is a three-dimensional (3D) stacked semiconductor device which includes: a 1 st source/drain region (135) connected to a 1 st channel structure (112); and a 2 nd source/drain region (145), above the 1 st source/drain region (135), connected to a 2 nd channel structure (122) above the 1 st channel structure (112), wherein the 2 nd channel structure (122) has a smaller length than the 1 st channel structure (112) in a channel-length direction (D1), in which the 2 nd source/drain region (145) is connected to a 3 rd source/drain region through the 2 nd channel structure (122).

公开(公告)号：EP4478424A1

公开(公告)日：2024-12-18

申请号：EP23770271.7

申请日：2023-02-17

Applicant: Nuvoton Technology Corporation Japan

Inventor： NISHIO, Akihiko ,  DOI, Hiroyuki

IPC: H01L29/812 ,  H01L21/28 ,  H01L21/338 ,  H01L21/822 ,  H01L27/04 ,  H01L29/41 ,  H01L29/417 ,  H01L29/778

Abstract: A semiconductor device for high-frequency amplification (100) includes a substrate (101); a first nitride semiconductor layer (103) above the substrate (101); a two-dimensional electron gas layer (105); a second nitride semiconductor layer (104); and a source electrode (301), a drain electrode (302), and a gate electrode (401) spaced apart from each other above the first nitride semiconductor layer (104). In a plan view, an active region (701) with a two-dimensional electron gas layer (105) includes a resistor (601) and the resistor (601) provided above the second nitride semiconductor layer (104). In the plan view, a non-active region (704) includes a drain terminal (803) and a gate terminal (804) connected to the drain electrode (302) or the gate electrode (401); and a first resistor terminal (805) and a second resistor terminal (806) connected to the resistor (601).

公开(公告)号：EP4459672A1

公开(公告)日：2024-11-06

申请号：EP24166819.3

申请日：2024-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUN, Seungchan ,  BAEK, Jaejik ,  SEO, Kang-Ill

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

Abstract: An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.

公开(公告)号：EP4451318A2

公开(公告)日：2024-10-23

申请号：EP24162335.4

申请日：2024-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SONG, Seung Min ,  LEE, Jaehong ,  SEO, Kang-Ill

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775

Abstract: An integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising a pair of upper source/drain regions spaced apart from each other in a first horizontal direction and an upper gate electrode between the pair of upper source/drain regions; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower gate electrode; an upper insulating layer on the lower transistor structure, wherein the upper gate electrode is in the upper insulating layer; and a lower gate contact extending through the upper insulating layer and contacting the lower gate electrode, a center of the upper gate electrode in a second horizontal direction and a center of the lower gate electrode in the second horizontal direction are offset from each other in the second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

公开(公告)号：EP4441783A1

公开(公告)日：2024-10-09

申请号：EP21824524.9

申请日：2021-12-02

Applicant: Imec VZW ,  Huawei Technologies Co., Ltd.

Inventor： CHEHAB, Bilal ,  BHUWALKA, Krishna, Kumar ,  RYCKAERT, Julien

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/775

CPC classification number: H01L21/82385 ,  H01L27/092 ,  H01L21/823871 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L27/0924 ,  H01L29/78696

公开(公告)号：EP4435844A1

公开(公告)日：2024-09-25

申请号：EP24164411.1

申请日：2024-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOO, Donggon

IPC: H01L21/822 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L23/48 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0688 ,  H01L21/76898 ,  H01L29/41725 ,  H01L29/66439 ,  H01L29/775 ,  H01L23/481 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L23/485 ,  H01L21/76805 ,  H01L21/76897

Abstract: A semiconductor device includes: insulating patterns; a device isolation layer on side surfaces of the insulating patterns; gate structures; source/drain regions (150) on the insulating patterns; a via structure (190) between the gate structures and between the source/drain regions; and contact structures (180) connected to the source/drain regions and the via structure, wherein the source/drain regions may include first source/drain regions (150A) and second source/drain regions (150B), wherein the via structure may extend from the same level as lower surfaces of the first source/drain regions to the same level as upper surfaces of the second source/drain regions, and the via structure may include a portion in which a width of the via structure increases and then decreases or decreases and then increases, wherein the contact structures may include a first contact structure contacting the first source/drain regions and a second contact structure contacting the second source/drain regions.

公开(公告)号：EP4425547A1

公开(公告)日：2024-09-04

申请号：EP22886470.8

申请日：2022-09-08

Applicant: Sony Semiconductor Solutions Corporation

Inventor： SHIGETOSHI, Takushi

IPC: H01L25/065 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L25/07 ,  H01L25/18 ,  H01L27/04 ,  H01L27/146

CPC classification number: H01L25/065 ,  H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L25/18 ,  H01L25/07 ,  H01L27/146 ,  H01L27/04

Abstract: A semiconductor device capable of improving integration of elements within a second element chip is provided.
A semiconductor device according to the present technology includes at least one first element chip, and at least one chip laminated with the first element chip and smaller than the first element chip. The at least one chip includes at least one second element chip. The first element chip has a laminated structure where a first semiconductor substrate and a first wiring layer are laminated. The second element chip has a laminated structure where a second semiconductor substrate and a second wiring layer are laminated. The first wiring layer and the second wiring layer are joined face-to-face with each other. The semiconductor device further includes an external connection terminal disposed at a position farther from the first element chip in a lamination direction than a rear surface of the chip, the rear surface being a surface on the side opposite to the first element chip and a wire that has at least a part disposed around the chip and electrically connects the first wiring layer and the external connection terminal.