A floating point number calculation circuit (100) and a floating point number calculation method are disclosed. A splitting circuit (102) included in the floating point number calculation circuit (100) splits a mantissa part of a first floating point number and a mantissa part of a second floating point number. An exponential processing circuit (104) obtains a second number of shifted bits of each mantissa part obtained after splitting. A calculation circuit (105) calculates a product of the mantissa part of the first floating point number and the mantissa part of the second floating point number based on each mantissa part obtained after splitting and the second number of shifted bits of each mantissa part obtained after splitting. The floating point number calculation circuit (100) can split a large bit-width floating point number into small bit-width floating point numbers, so that a small bit-width multiplier is used to calculate the large bit-width floating point number. The floating point number calculation circuit (100) provided in this application has small timing overheads and low hardware design costs. Therefore, calculation performance of the multiplier is appropriately used.