- 专利标题: LOW GATE-COUNT ENCODING ALGORITHM AND HARDWARE OF FLEXIBLE RATE GLDPC ECC
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申请号: EP23153232.6申请日: 2023-01-25
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公开(公告)号: EP4250117A1公开(公告)日: 2023-09-27
- 发明人: KISSOS, Lior , SHANY, Yaron , BERMAN, Amit , DOUBCHAK, Ariel
- 申请人: Samsung Electronics Co., Ltd.
- 申请人地址: KR Gyeonggi-do 16677 129, Samsung-ro Yeongtong-gu Suwon-si
- 代理机构: Kuhnen & Wacker Patent- und Rechtsanwaltsbüro PartG mbB
- 优先权: US202217702048 20220323
- 主分类号: G06F11/08
- IPC分类号: G06F11/08 ; G06F11/10 ; H03M13/11 ; H03M13/29 ; H03M13/00
摘要:
Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.
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