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公开(公告)号:EP4460760A1
公开(公告)日:2024-11-13
申请号:EP22838862.5
申请日:2022-12-22
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公开(公告)号:EP4460758A1
公开(公告)日:2024-11-13
申请号:EP22823101.5
申请日:2022-12-02
IPC分类号: G06F11/10 , G06K7/14 , G06K19/06 , H03M13/15 , G06F16/955
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公开(公告)号:EP4457627A1
公开(公告)日:2024-11-06
申请号:EP22917167.3
申请日:2022-11-29
申请人: INTEL Corporation
发明人: LANKA, Narasimha , DAS SHARMA, Debendra , SESHAN, Lakshmipriya , CHOUDHARY, Swadesh , WU, Zuoguo , PASDAST, Gerald
IPC分类号: G06F11/10 , H01L25/065 , G06F13/40 , G06F11/07
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公开(公告)号:EP4446893A1
公开(公告)日:2024-10-16
申请号:EP24165870.7
申请日:2024-03-25
发明人: KIM, Jongmin , UM, Kyungsik , OH, Minsik , KANG, Donggil , SONG, Jinwoo , JEONG, Myunggwan , CHO, Kyungjune
IPC分类号: G06F11/10
摘要: A method of operating a storage device using a host memory buffer of a host includes: recording information on HMB addresses on the host memory buffer, respectively corresponding to a plurality of read requests for the host memory buffer, in an address information table when the plurality of read requests are required; transmitting the plurality of read requests to the host memory buffer, regardless of a response of the host memory buffer; receiving a plurality of pieces of read data, respectively corresponding to the plurality of read requests, from the host memory buffer; detecting an error of each of the plurality of pieces of read data; and updating the address information table based on a result of the error detection.
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公开(公告)号:EP4437417A1
公开(公告)日:2024-10-02
申请号:EP22896362.5
申请日:2022-11-14
申请人: Rambus Inc.
发明人: SONG, Taeksang
CPC分类号: G06F11/07 , G06F11/1048
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公开(公告)号:EP4404063A3
公开(公告)日:2024-09-25
申请号:EP23188114.5
申请日:2023-07-27
申请人: Kioxia Corporation
发明人: Nakatsuka, Hiroyasu , Nagai, Koichi
IPC分类号: G06F11/10
CPC分类号: G06F11/108 , G06F11/1076
摘要: According to one embodiment, an information processing system includes a host (2) and memory systems (3). A first memory system stores first data in a nonvolatile memory (5). A second memory system stores second data in a nonvolatile memory (5). The host (2) transmits first update data to the first memory system and transmits second update data to the second memory system. The first memory system generates first XOR data by performing an XOR operation on at least the first data and the first update data, and transmits the first XOR data to the second memory system. The second memory system generates second XOR data by performing an XOR operation on the second data, the second update data, and the first XOR data, and transmits the second XOR data to a third memory system.
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公开(公告)号:EP4432090A1
公开(公告)日:2024-09-18
申请号:EP24163238.9
申请日:2024-03-13
发明人: HWANG, Jinwoo
IPC分类号: G06F11/10
CPC分类号: G06F11/1004
摘要: A cyclic redundancy check (CRC) system and a CRC method are provided. The CRC system includes a data folding processing circuit and a CRC processing circuit. The data folding processing circuit includes a first bit fold circuit configured to fold first input data into first fold data, a second bit fold circuit configured to fold second input data into second fold data, and a stream fold circuit configured to generate first fold streaming data based on the first fold data and the second fold data. The CRC processing circuit includes a first flip-flop configured to receive and store first dividend data of a first cycle, a second flip-flop configured to receive and store the first fold streaming data of the first cycle, and a CRC logic configured to perform a CRC operation on the first dividend data and the first fold streaming data.
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公开(公告)号:EP4430474A1
公开(公告)日:2024-09-18
申请号:EP22893470.9
申请日:2022-10-28
IPC分类号: G06F11/10 , G06F11/30 , G06F11/22 , G06F11/277 , G06N3/08
CPC分类号: G11C29/52 , G11C29/022 , G11C29/028
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公开(公告)号:EP4266178B1
公开(公告)日:2024-09-18
申请号:EP23168346.7
申请日:2023-04-17
CPC分类号: G06F11/1048 , G06F11/2215
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公开(公告)号:EP4425497A1
公开(公告)日:2024-09-04
申请号:EP24159195.7
申请日:2024-02-22
发明人: LENG, Qiuming , MORDECAI, Billy J.
CPC分类号: G11C29/42 , G11C2029/041120130101 , G06F11/10 , G11C29/76
摘要: A computer system operates a method of detecting and handling a RAM parity error in the context of a RAM test. The computer system includes a memory storing therein a lookup table having a plurality of entries, each entry including a data location and a RAM parity error handler type. A processor obtains an address of a faulty byte detected during a RAM test on the parity RAM, searches the lookup table for an entry that contains the faulty byte based on the address of the faulty byte, obtains the RAM parity error handler type from the entry, and fixes a data field impacted by the faulty byte based on the RAM parity error handler type.
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