The present disclosure discloses a method for optimizing matrix multiplication of an on-chip system and related products. The on-chip system is included in a computing processing apparatus of a combined processing apparatus. The computing processing apparatus includes one or a plurality of integrated circuit apparatuses. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing processing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is configured to store data of the apparatus and other processing apparatus. The solution of the present disclosure may reduce the amount of data transmission between an internal device and an external storage apparatus, thus minimizing the I/O bottleneck caused by bandwidth limitations and then improving overall performance of an integrated circuit apparatus.