- 专利标题: COMPUTER PROCESSOR FOR HIGHER PRECISION COMPUTATIONS USING A MIXED-PRECISION DECOMPOSITION OF OPERATIONS
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申请号: EP24152035.2申请日: 2019-06-25
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公开(公告)号: EP4328744A3公开(公告)日: 2024-04-17
- 发明人: Henry, Gregory , Heinecke, Alexander
- 申请人: INTEL Corporation
- 申请人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 专利权人: INTEL Corporation
- 当前专利权人: INTEL Corporation
- 当前专利权人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 代理机构: Samson & Partner Patentanwälte mbB
- 优先权: US 201816144964 2018.09.27
- 分案原申请号: 22167262.9 2022.04.08;19182449.9 2019.06.25
- 主分类号: G06F7/48
- IPC分类号: G06F7/48 ; G06F7/483 ; G06F7/57 ; G06F7/487 ; G06F9/30
摘要:
Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes a plurality of cores to execute instructions. Each core of the plurality of cores comprises: a Level-1 (L1) instruction cache to store the instructions and an L1 data cache to store corresponding data; a plurality of vector registers to store a plurality of packed data elements, including single-precision floating-point data elements and reduced precision floating-point data elements having fewer mantissa bits than the single-precision floating point data elements and a same number of exponent bits as the single-precision floating point format data elements; and execution circuitry to execute an instruction to generate a dot product with a first pair of the reduced precision floating-point data elements and a corresponding second pair of the reduced precision floating-point data elements. The execution circuitry is to: generate a plurality of single precision floating-point products corresponding to the first pair and the second pair of the reduced precision floating-point data elements; and accumulate the plurality of single precision floating-point products to generate a single precision floating-point result data element.
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