发明公开
- 专利标题: GATE LINE PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
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申请号: EP23220365.3申请日: 2018-10-30
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公开(公告)号: EP4328973A3公开(公告)日: 2024-05-29
- 发明人: HO, Byron , HATTENDORF, Michael L. , AUTH, Christopher P.
- 申请人: INTEL Corporation
- 申请人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 专利权人: INTEL Corporation
- 当前专利权人: INTEL Corporation
- 当前专利权人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 代理机构: Goddar, Heinz J.
- 优先权: US 201762593149 P 2017.11.30
- 分案原申请号: 18203569.1 2018.10.30
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L29/66 ; H01L29/78 ; H01L27/088 ; H01L21/033 ; H01L21/308 ; H01L21/762 ; H01L21/768 ; H01L21/8238 ; H01L23/485 ; H01L23/522 ; H01L23/532 ; H01L27/092 ; H01L29/165 ; H01L29/417
摘要:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.
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