A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, wherein the first metallization layer comprises a plurality of different sections that are separate and distinct from each other, and a plurality of semiconductor bodies arranged on the first metallization layer, wherein a first electrode of each of the plurality of semiconductor bodies is electrically coupled to a first section of the first metallization layer, a second electrode of each of the plurality of semiconductor bodies is electrically coupled to a second section of the first metallization layer, a third electrode of each of the plurality of semiconductor bodies is electrically coupled to an additional metallization layer by means of one or more electrical connection elements, the additional metallization layer is arranged distant from and in parallel to the first metallization layer, and the additional metallization layer is arranged on an additional dielectric insulation layer, wherein the additional dielectric insulation layer is arranged in parallel to and distant from the dielectric insulation layer, and wherein the additional dielectric insulation layer is arranged between the additional metallization layer and the first metallization layer.