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    THERMAL PERFORMANCE IMPROVEMENT AND STRESS REDUCTION IN SEMICONDUCTOR DEVICE MODULES
    1.
    发明公开
    THERMAL PERFORMANCE IMPROVEMENT AND STRESS REDUCTION IN SEMICONDUCTOR DEVICE MODULES 审中-公开

    公开(公告)号：EP4471846A3

    公开(公告)日：2025-02-26

    申请号：EP24207811.1

    申请日：2023-03-13

    Applicant: Semiconductor Components Industries, LLC

    Inventor： LIU, Yong ,  YANG, Quing

    IPC: H01L23/373 ,  H05K1/02 ,  H01L23/31 ,  H05K3/00 ,  H05K7/20 ,  H05K7/14 ,  H01L25/07 ,  H01L23/498 ,  H01L23/00

    Abstract: In some aspects, the techniques described herein relate to a signal distribution assembly configured to conduct signals in a semiconductor device module, the signal distribution assembly including: a metal layer, the metal layer having: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and including: a base portion; a first post extending from the base portion; and a second post extending from the base portion. The metal layer can be pre-molded using a molding compound disposed on the second side of the metal later, with respective surfaces of the first post and the second posted exposed through the molding compound, and or the metal layer can be coupled with a thermally conductive insulator (e.g., ceramic) layer.

    SEMICONDUCTOR PACKAGE AND INTEGRATED CIRCUIT DEVICE
    3.
    发明公开
    SEMICONDUCTOR PACKAGE AND INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：EP4510186A1

    公开(公告)日：2025-02-19

    申请号：EP24168505.6

    申请日：2024-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YU, Bong Wee ,  KIM, Chang Soo ,  JEON, Byung Chul ,  HUH, Jun Ho

    IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18

    Abstract: A semiconductor package is provided. The semiconductor package comprises a package substrate, a first semiconductor chip on the package substrate, a second semiconductor chip spaced apart from the first semiconductor chip on the package substrate, and a bridge die placed below the first semiconductor chip and the second semiconductor chip on the package substrate, wherein the bridge die includes a first face that faces the first semiconductor chip and the second semiconductor chip, a second face that faces the package substrate, a connection wiring structure which is placed on the first face, and connects the first semiconductor chip and the second semiconductor chip, and a power wiring structure which is placed on the second face, and provides power to the first semiconductor chip and the second semiconductor chip.

    TERMINAL ELEMENT, AND POWER SEMICONDUCTOR MODULE ARRANGEMENT COMPRISING A TERMINAL ELEMENT
    4.
    发明公开
    TERMINAL ELEMENT, AND POWER SEMICONDUCTOR MODULE ARRANGEMENT COMPRISING A TERMINAL ELEMENT 审中-公开

    公开(公告)号：EP4510184A1

    公开(公告)日：2025-02-19

    申请号：EP23192162.8

    申请日：2023-08-18

    Applicant: Infineon Technologies AG

    Inventor： CHAJNETA, Michal ,  TAKKAC, Alparslan ,  FROEBUS, Dirk

    IPC: H01L23/498

    Abstract: A terminal element for a power semiconductor module arrangement comprises a first end (41) configured to be arranged inside a housing (7) of the power semiconductor module arrangement (100), a second end (42) configured to be arranged outside of the housing (7) of the power semiconductor module arrangement (100), a first section (410) and a second section (420) arranged successively between the first end (41) and the second end (42) along a length (l4) of the terminal element (4), and a third section (430) arranged between the first section (410) and the second section (420), wherein the first section (410) has a first width (w410), the second section (420) extends in a first direction (z) and has a second width (w420) that is greater than the first width (w410), and the third section (430) has a width greater than the first width (w410), and extends in a second direction (y) which is angled relative to the first direction (z).

    PAD STRUCTURES FOR SEMICONDUCTOR DEVICES
    5.
    发明公开
    PAD STRUCTURES FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：EP4462483A3

    公开(公告)日：2025-02-19

    申请号：EP24203225.8

    申请日：2020-09-02

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： XIAO, Liang ,  WU, Shu

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18

    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first die and a second die boned face-to-face. The first die includes first transistors formed on a face side of the first die in a semiconductor portion and at least a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a substrate and second transistors formed on a face side of the second die. Further, the semiconductor device includes a first pad structure disposed on a back side of the first die and the first pad structure is conductively coupled with the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. Further, in some embodiments, the semiconductor device includes a connection structure disposed on the back side of the first die and conductively connected with the semiconductor portion.

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