Embodiments of the present disclosure provide a parallel decoding method, a processor, a chip, and an electronic device. The processor at least comprises a first decoder group and a second decoder group, and the second decoder group is provided with at least one shared decoder shared by the first decoder group. The method comprises: selecting a plurality of instructions from a first instruction queue corresponding to a first decoder group; if the number of the plurality of instructions is greater than the number of decoders in the first decoder group, allocating first instructions, corresponding to the number of decoders in the first decoder group, in the plurality of instructions to the decoders in the first decoder group for decoding, and allocating second instructions other than the first instructions in the plurality of instructions to the shared decoder for decoding; and writing micro-instructions obtained by decoding the first instructions by the first decoder group, and micro-instructions obtained by decoding the second instructions by the shared decoder into a first micro-instruction queue. The embodiments of the present disclosure can save hardware resources of a processor while the decoding throughput is guaranteed.