公开(公告)号：EP4459460A1

公开(公告)日：2024-11-06

申请号：EP23884473.2

申请日：2023-09-13

申请人： Hygon Information Technology Co., Ltd.

发明人： CUI, Zehan

IPC分类号： G06F9/38

摘要： Embodiments of the present disclosure provide a decoding method for a multi-thread processor, a processor, a chip, and an electronic device. The method comprises: fetching an instruction stream according to an instruction fetch request; splitting the fetched instruction stream in response to a multi-thread processor being in a single-threaded mode; using instructions at split positions as boundaries of switching instruction queues, and distributing the split instruction stream to a plurality of target instruction queues, wherein the plurality of target instruction queues comprise instruction queues corresponding to active threads and instruction queues corresponding to inactive threads; and decoding the instructions in the plurality of target instruction queues by using a plurality of decoder groups to obtain micro-ops obtained after decoding by the decoder groups. The embodiments of the present disclosure can improve the decoding efficiency of a multi-thread processor while being compatible with multiple thread modes.

公开(公告)号：EP4428682A1

公开(公告)日：2024-09-11

申请号：EP23884010.2

申请日：2023-02-27

申请人： Hygon Information Technology Co., Ltd.

发明人： CUI, Zehan

IPC分类号： G06F9/38

CPC分类号： Y02D10/00

摘要： Embodiments of the present disclosure provide a parallel decoding method, a processor, a chip, and an electronic device. The processor at least comprises a first decoder group and a second decoder group, and the second decoder group is provided with at least one shared decoder shared by the first decoder group. The method comprises: selecting a plurality of instructions from a first instruction queue corresponding to a first decoder group; if the number of the plurality of instructions is greater than the number of decoders in the first decoder group, allocating first instructions, corresponding to the number of decoders in the first decoder group, in the plurality of instructions to the decoders in the first decoder group for decoding, and allocating second instructions other than the first instructions in the plurality of instructions to the shared decoder for decoding; and writing micro-instructions obtained by decoding the first instructions by the first decoder group, and micro-instructions obtained by decoding the second instructions by the shared decoder into a first micro-instruction queue. The embodiments of the present disclosure can save hardware resources of a processor while the decoding throughput is guaranteed.

公开(公告)号：EP4425327A1

公开(公告)日：2024-09-04

申请号：EP23884011.0

申请日：2023-02-27

申请人： Hygon Information Technology Co., Ltd.

发明人： CUI, Zehan

IPC分类号： G06F9/38

CPC分类号： Y02D10/00

摘要： Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method comprises: generating an instruction fetch request carrying at least one switching mark, the switching mark at least indicating an instruction position for decoder group switching; in response to micro-ops obtained from decoding by decoder groups, acquiring an instruction stream fetched by means of the instruction fetch request, and according to the switching mark carried in the instruction fetch request, determining the instruction position for decoder group switching; according to the instruction position, distributing the instruction stream to multiple decoder groups for parallel decoding, and carrying a switching mark in a target micro-op obtained by decoding a target instruction, the target instruction being an instruction corresponding to the instruction position; and in response to searching a micro-op cache for micro-ops, if the instruction fetch request is hit in the micro-op cache, acquiring a corresponding micro-op from the micro-op cache. The embodiments of the present disclosure can improve the decoding performance of a processor.