A semiconductor device (100) includes a substrate (101) having active regions (105) extending in a first direction (x), a device isolation layer (110) in the substrate (101) between the active regions (105) and exposing upper surfaces of the active regions (105), gate structures (160) on the active regions, intersecting the active regions and extending in a second direction (y), source/drain regions (150) adjacent to the gate structure (160) and on the active region (105), contact plugs (170) on the source/drain region (150), the contact plugs extending into respective recesses in the source/drain regions and electrically connected to the source/drain regions (150), a first power structure (VS1) between adjacent source/drain region (150) in the second direction (y) and electrically connected to at least one of the contact plugs (170), and a second power structure (VS2) penetrating the substrate (101) and on a lower end of the first power structure (VS1), and a lateral dielectric layer (155) on surfaces of the source/drain regions (105) and extending along an upper surface of the device isolation layer (110) and on a first portion of a side surface of the first power structure (VS1). The first power structure (VS1) has a first width (W1) at an upper thereof and a second width (W2) at the lower end thereof, the second width being equal to or greater than the first width.