公开(公告)号：EP4435859A2

公开(公告)日：2024-09-25

申请号：EP23214718.1

申请日：2023-12-06

申请人： Intel Corporation

发明人： CHU, Tao ,  JANG, Minwoo ,  LUO, Yanbin ,  PACKAN, Paul ,  XU, Guowei ,  HUANG, Chiao-Ti ,  CHAO, Robin ,  ZHANG, Feng ,  MURTHY, Anand S. ,  GHANI, Tahir

IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L27/118

CPC分类号： H01L2027/1187520130101 ,  H01L27/0207 ,  H01L21/823475

摘要： An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.

公开(公告)号：EP4418320A1

公开(公告)日：2024-08-21

申请号：EP23191650.3

申请日：2023-08-16

申请人： GlobalFoundries U.S. Inc.

发明人： Pritchard, David Charles ,  Mazza, James P. ,  Jain, Navneet K. ,  Yu, Hong

IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L21/8238

CPC分类号： H01L27/0207 ,  H01L27/11807 ,  H01L2027/1186620130101 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823871 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092

摘要： A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.

公开(公告)号：EP4407682A1

公开(公告)日：2024-07-31

申请号：EP24151575.8

申请日：2024-01-12

申请人： Samsung Electronics Co., Ltd.

发明人： CHO, Yongeun ,  CHOI, Eunhee ,  KIM, Kibum ,  KIM, Seonkyeong ,  KIM, Hayoung ,  ROH, Hyunjeong ,  BAE, Moogyu

IPC分类号： H01L27/02 ,  G06F30/392 ,  H01L27/118

CPC分类号： H01L27/0207 ,  H01L2027/1187520130101 ,  H01L27/11807 ,  G06F30/392

摘要： An integrated circuit includes a first region having a plurality of first cells arranged in first rows extending in a first direction and a plurality of first gate electrodes extending in a second direction that crosses the first direction, a second region having a plurality of second cells arranged in second rows extending in the first direction and a plurality of second gate electrodes extending in the second direction, and a third region between the first region and the second region and having a plurality of third gate electrodes extending in the second direction. A second height of each of the second rows is greater than a first height of each of the first rows. A pitch of the first gate electrodes, a pitch of the second gate electrodes, and a pitch of the third gate electrodes are the same.

公开(公告)号：EP4406027A1

公开(公告)日：2024-07-31

申请号：EP22783245.8

申请日：2022-09-09

申请人： Advanced Micro Devices, Inc.

发明人： SCHULTZ, Richard T.

IPC分类号： H01L27/02 ,  G06F30/394 ,  H01L23/528 ,  H01L27/118

CPC分类号： H01L27/0207 ,  H01L23/5286 ,  G06F30/394 ,  H01L2027/1183720130101 ,  H01L2027/1188120130101 ,  H01L2027/1187520130101 ,  H01L27/11807

公开(公告)号：EP4398299A1

公开(公告)日：2024-07-10

申请号：EP23195592.3

申请日：2023-09-06

申请人： GlobalFoundries U.S. Inc.

发明人： Mazza, James P. ,  Zeng, Jia ,  Zhu, Xuelian ,  Jain, Navneet K. ,  Rashed, Mahbub ,  Mazza, Jacob

IPC分类号： H01L27/02 ,  G06F30/392 ,  H01L27/118

CPC分类号： H01L27/0207 ,  H01L2027/1187520130101 ,  G06F30/392 ,  H01L2027/1188120130101

摘要： A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：EP4386844A2

公开(公告)日：2024-06-19

申请号：EP23207935.0

申请日：2023-11-06

申请人： Samsung Electronics Co., Ltd.

发明人： HWANG, Junsun ,  PARK, Sewoong ,  LEE, JeongHo

IPC分类号： H01L27/02 ,  H01L21/8238 ,  H01L29/775 ,  H01L27/118

CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L29/775 ,  H01L2027/1187520130101

摘要： Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a cell disposing region and a first block border region, a plurality of gate electrodes on the cell disposing region and extending to the first block border region in a first direction to be parallel to each other, the gate electrodes including a first and second gate electrode, which are adjacent to each other, and a first connection structure on the first block border region, wherein the first connection structure is configured to physically connect the first and second gate electrodes to each other.

公开(公告)号：EP4386842A1

公开(公告)日：2024-06-19

申请号：EP23196236.6

申请日：2023-09-08

申请人： Kioxia Corporation

发明人： Kohara, Koji

IPC分类号： H01L27/02 ,  G06F30/392 ,  H01L23/528 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F30/392 ,  H01L23/5286 ,  H01L2027/1187520130101 ,  H01L2027/1188120130101

摘要： According to one embodiment, a semiconductor integrated circuit includes: a first power supply line extending in a first direction; a second power supply line extending in the first direction parallel to the first power supply line; a block circuit disposed between the first and second power supply lines, and comprising a first logic circuit to which first and second inputs are supplied, a second logic circuit to which third and fourth inputs are supplied, and a third logic circuit to which outputs from the first and second logic circuits are supplied; a first wiring extending in a second direction orthogonal to the first direction; and a second wiring extending in the second direction parallel to the first wiring. Any one of the first or second input is connected to the first wiring, and any one of the third or fourth input is connected to the second wiring.

公开(公告)号：EP4148783B1

公开(公告)日：2024-05-29

申请号：EP22178041.4

申请日：2022-06-09

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/118 ,  H01L29/775 ,  H01L29/06 ,  H01L21/033

CPC分类号： H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L21/76816 ,  H01L21/823814 ,  H01L2027/1187520130101 ,  H01L27/092 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/0847 ,  H01L21/0337 ,  H01L23/5283

公开(公告)号：EP4236078A3

公开(公告)日：2023-09-06

申请号：EP23172682.9

申请日：2016-01-13

申请人： QUALCOMM Incorporated

发明人： SAHU, Satyanarayana ,  PUCKETT, Joshua Lance ,  KWON, Ohsang ,  GOODALL III, William James ,  BOWERS, Benjamin John

IPC分类号： H01L27/118 ,  H03K19/0175 ,  H03K19/20 ,  H03K19/17728 ,  H03K19/17736 ,  H01L27/02

摘要： At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

公开(公告)号：EP2533286B1

公开(公告)日：2023-09-06

申请号：EP12167829.6

申请日：2012-05-14

发明人： Abe, Kazuhiro

IPC分类号： H01L27/02 ,  H01L27/118