Invention Patent
- Patent Title: Semiconductor device manufacturing method
- Patent Title (中): 半导体器件制造方法
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Application No.: JP2012190993Application Date: 2012-08-31
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Publication No.: JP2014049592APublication Date: 2014-03-17
- Inventor: SUGIYAMA MICHIAKI , KINOSHITA YOSHIHIRO
- Applicant: Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
- Assignee: Renesas Electronics Corp,ルネサスエレクトロニクス株式会社
- Current Assignee: Renesas Electronics Corp,ルネサスエレクトロニクス株式会社
- Priority: JP2012190993 2012-08-31
- Main IPC: H01L25/18
- IPC: H01L25/18 ; H01L25/065 ; H01L25/07
Abstract:
PROBLEM TO BE SOLVED: To prevent an excess stress from being applied to a connection part of two semiconductor chips in a semiconductor device in which a chip laminate including a small-diameter semiconductor chip and a large-diameter semiconductor chip is mounted on a top face of a base material.SOLUTION: In a semiconductor device manufacturing method, by mounting a large-diameter first semiconductor chip on a support substrate and subsequently mounting a small-diameter second semiconductor chip on the first semiconductor chip, since a tilt and slip of the second semiconductor chip mounted on the first semiconductor chip can be inhibited, an excess stress can be inhibited from being applied to a connection part of the first semiconductor chip and the second semiconductor chip.
Public/Granted literature
- JP6100489B2 半導体装置の製造方法 Public/Granted day:2017-03-22
Information query
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